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avance logic inc. ALS300 1 ALS300 media audio controller spec product number : rl5305 date: mar, 26,1999 copyright (c) 1997~1999,realtek semiconductor, inc. confidential & proprietary designer : davis kung features : z high performance pci digital audio subsystem controller. z sound blaster pro/16 emulation z support audio codec 97 specifications. z wave engine with wave sample downloadable. z support 1m x 4 ,4m x 4 dram. z normal and enhanced game port z 16 bit full-duplex playback/recording z full-duplex digital modem line io from ac97 interface. z power down mode for notebook applic ation. z build-in fm compatible synthesizer. z optional external e 2 prom support. applications : z windows and mpc level 2 compatible audio subsystem. z pc games. z computer based audio reproduction z audio on-line tutorial z voice annotation or voice e-mail interface. z voice recognition or voice command controller. z text to speech. z karaoke/music sound box. z midi controller. z software modem. ALS300 pin descriptions: 128/160 pin qfp package pci bus interface signal : 48 pins pin name type p-160 p-128 description characteristic definition ad0 i/o 59 50 pci address/data bit 0 6ma ttl compatible cmos io (vt=1.7v) ad1 i/o 57 49 pci address/data bit 1 6ma ttl compatible cmos io (vt=1.7v) ad2 i/o 56 48 pci address/data bit 2 6ma ttl compatible cmos io (vt=1.7v) ad3 i/o 55 47 pci address/data bit 3 6ma ttl compatible cmos io (vt=1.7v) ad4 i/o 53 46 pci address/data bit 4 6ma ttl compatible cmos io (vt=1.7v) ad5 i/o 52 45 pci address/data bit 5 6ma ttl compatible cmos io (vt=1.7v) ad6 i/o 51 44 pci address/data bit 6 6ma ttl compatible cmos io (vt=1.7v) ad7 i/o 49 43 pci address/data bit 7 6ma ttl compatible cmos io (vt=1.7v) ad8 i/o 46 41 pci address/data bit 8 6ma ttl compatible cmos io (vt=1.7v) ad9 i/o 45 40 pci address/data bit 9 6ma ttl compatible cmos io (vt=1.7v) ad10 i/o 43 39 pci address/data bit 10 6ma ttl compatible cmos io (vt=1.7v) ad11 i/o 38 33 pci address/data bit 11 6ma ttl compatible cmos io (vt=1.7v) ad12 i/o 36 32 pci address/data bit 12 6ma ttl compatible cmos io (vt=1.7v) ad13 i/o 35 31 pci address/data bit 13 6ma ttl compatible cmos io (vt=1.7v) ad14 i/o 34 30 pci address/data bit 14 6ma ttl compatible cmos io (vt=1.7v) ad15 i/o 32 29 pci address/data bit 15 6ma ttl compatible cmos io (vt=1.7v) ad16 i/o 17 17 pci address/data bit 16 6ma ttl compatible cmos io (vt=1.7v) ad17 i/o 15 16 pci address/data bit 17 6ma ttl compatible cmos io (vt=1.7v) ad18 i/o 14 15 pci address/data bit 18 6ma ttl compatible cmos io (vt=1.7v) ad19 i/o 13 14 pci address/data bit 19 6ma ttl compatible cmos io (vt=1.7v) ad20 i/o 11 12 pci address/data bit 20 6ma ttl compatible cmos io (vt=1.7v) ad21 i/o 10 11 pci address/data bit 21 6ma ttl compatible cmos io (vt=1.7v)
avance logic inc. ALS300 2 ad22 i/o 9 10 pci address/data bit 22 6ma ttl compatible cmos io (vt=1.7v) ad23 i/o 7 9 pci address/data bit 23 6ma ttl compatible cmos io (vt=1.7v) ad24 i/o 3 6 pci address/data bit 24 6ma ttl compatible cmos io (vt=1.7v) ad25 i/o 158 128 pci address/data bit 25 6ma ttl compatible cmos io (vt=1.7v) ad26 i/o 156 127 pci address/data bit 26 6ma ttl compatible cmos io (vt=1.7v) ad27 i/o 155 126 pci address/data bit 27 6ma ttl compatible cmos io (vt=1.7v) ad28 i/o 153 125 pci address/data bit 28 6ma ttl compatible cmos io (vt=1.7v) ad29 i/o 152 124 pci address/data bit 29 6ma ttl compatible cmos io (vt=1.7v) ad30 i/o 150 123 pci address/data bit 30 6ma ttl compatible cmos io (vt=1.7v) ad31 i/o 149 122 pci address/data bit 31 6ma ttl compatible cmos io (vt=1.7v) c/be0 i/o 48 42 pci command/byte enable bit 0 6ma ttl compatible cmos io (vt=1.7v) c/be1 i/o 31 28 pci command/byte enable bit 1 6ma ttl compatible cmos io (vt=1.7v) c/be2 i/o 18 18 pci command/byte enable bit 2 6ma ttl compatible cmos io (vt=1.7v) c/be3 i/o 5 7 pci command/byte enable bit 3 6ma ttl compatible cmos io (vt=1.7v) frame# i/o 22 20 pci cycle frame 8ma ttl compatible cmos io (vt=1.7v) irdy# i/o 23 21 pci initiator ready 8ma ttl compatible cmos io (vt=1.7v) trdy# i/o 26 23 pci target ready 8ma ttl compatible cmos io (vt=1.7v) stop# i/o 28 25 pci stop 8ma ttl compatible cmos io (vt=1.7v) idsel i 6 8 pci initialization device select ttl compatible cmos input devsel# i/o 27 24 pci device select 8ma ttl compatible cmos io (vt=1.7v) clk i 143 117 pci system clock(33mhz) ttl compatible cmos input rst# i 141 115 pci system reset schmitt triggered cmos input (1.4v-2.2v) par i/o 30 26 pci parity 6ma ttl compatible cmos io (vt=1.7v) req# o 148 121 pci request 6ma ttl compatible cmos output (vt=1.7v) gnt# i 146 120 pci grant ttl compatible cmos input (vt=1.7v) inta# o 140 114 pci interrupt request a 6ma ttl compatible cmos output (vt=1.7v) ac97 interface signal : 5 pins pin name type p-160 p-128 description characteristic definition sync o 133 110 48khz fixed rate sample sync 12ma ttl compatible cmos output (vt=1.7v) bit_clk i 136 112 12.288mhz serial bit clock ttl compatible cmos input (vt=1.7v) sd_out o 137 113 ac97 serial output stream 12ma ttl compatible cmos output (vt=1.7v) sd_in i 135 111 ac97 serial input stream ttl compatible cmos input (vt=1.7v) reset# o 132 109 ac97 reset 4ma ttl compatible cmos output (vt=1.7v) isa interface : 38 pins (enabled when bond=0) pin name type p-160 p-128 description characteristic definition sa0 i 33 * isa system address bit 0 ttl input (vt=1.7v) sa1 i 37 * isa system address bit 1 ttl input (vt=1.7v) sa2 i 44 * isa system address bit 2 ttl input (vt=1.7v) sa3 i 47 * isa system address bit 3 ttl input (vt=1.7v) sa4 i 50 * isa system address bit 4 ttl input (vt=1.7v) sa5 i 54 * isa system address bit 5 ttl input (vt=1.7v) sa6 i 58 * isa system address bit 6 ttl input (vt=1.7v) sa7 i 63 * isa system address bit 7 ttl input (vt=1.7v) sa8 i 67 * isa system address bit 8 ttl input (vt=1.7v) sa9 i 71 * isa system address bit 9 ttl input (vt=1.7v) sa10 i 74 * isa system address bit 10 ttl input (vt=1.7v) sa11 i 77 * isa system address bit 11 ttl input (vt=1.7v) sa12 i 84 * isa system address bit 12 ttl input (vt=1.7v) sa13 i 87 * isa system address bit 13 ttl input (vt=1.7v) sa14 i 90 * isa system address bit 14 ttl input (vt=1.7v) sa15 i 94 * isa system address bit 15 ttl input (vt=1.7v) saen i 110 * isa system address enable ttl input (vt=1.7v) sd0 io 126 * isa system data bus bit 0 4ma ttl compatible cmos io (vt=1.7v) sd1 io 128 * isa system data bus bit 1 4ma ttl compatible cmos io (vt=1.7v) sd2 io 130 * isa system data bus bit 2 4ma ttl compatible cmos io (vt=1.7v) sd3 io 134 * isa system data bus bit 3 4ma ttl compatible cmos io (vt=1.7v) sd4 io 138 * isa system data bus bit 4 4ma ttl compatible cmos io (vt=1.7v) sd5 io 145 * isa system data bus bit 5 4ma ttl compatible cmos io (vt=1.7v) sd6 io 147 * isa system data bus bit 6 4ma ttl compatible cmos io (vt=1.7v) sd7 io 151 * isa system data bus bit 7 4ma ttl compatible cmos io (vt=1.7v) siow# i 154 * isa io write strobe schmitt triggered cmos input (1.2v-2.6v)
avance logic inc. ALS300 3 sior# i 157 * isa io read strobe schmitt triggered cmos input (1.2v-2.6v) drq0 o 25 * isa dma request 0 4ma cmos output with tri-state control drq1 o 16 * isa dma request 1 4ma cmos output with tri-state control drq3 o 8 * isa dma request 3 4ma cmos output with tri-state control dack0# i 29 * isa dma acknowledge 0 cmos input (vt=2.0v) dack1# i 12 * isa dma acknowledge 1 cmos input (vt=2.0v) dack3# i 4 * isa dma acknowledge 3 cmos input (vt=2.0v) irq2/9 o 113 * isa interrupt request 2/9 4ma cmos open drain output irq5 o 101 * isa interrupt request 5 4ma cmos open drain output irq7 o 105 * isa interrupt request 7 4ma cmos open drain output irq10 o 20 * isa interrupt request 10 4ma cmos open drain output irq11 o 96 * isa interrupt request 11 4ma cmos open drain output game port/midi interface signal : 10 pins pin name type p-160 p-128 description characteristic definition midi_in i 131 108 midi serial input schmitt triggered cmos input with 10k w pull up (1.7v- 2.7v) midi_out o 129 107 midi serial output 8ma cmos io with 50k w pull up (vt=1.7v) gd0 i/o 107 88 game port a timer x 8ma schmitt triggered cmos io (2.0v-3.0v) gd1 i/o 106 87 game port a timer y 8ma schmitt triggered cmos io (2.0v-3.0v) gd2 i/o 104 86 game port b timer x 8ma schmitt triggered cmos io (2.0v-3.0v) gd3 i/o 103 85 game port b timer y 8ma schmitt triggered cmos io (2.0v-3.0v) gd4 i 102 84 game port a button a schmitt triggered cmos input with 10k w pull up (2.0v- 3.0v) gd5 i 100 83 game port a button b schmitt triggered cmos input with 10k w pull up (2.0v- 3.0v) gd6 i 99 82 game port b button a schmitt triggered cmos input with 10k w pull up (2.0v- 3.0v) gd7 i 97 80 game port b button b schmitt triggered cmos input with 10k w pull up (2.0v- 3.0v) dram interface signal : 20 pins pin name type p-160 p-128 description characteristic definition a0 o 92 77 dram address bit 0 4ma ttl compatible cmos output (vt=1.7v) a1 o 91 76 dram address bit 1 4ma ttl compatible cmos output (vt=1.7v) a2 o 89 75 dram address bit 2 4ma ttl compatible cmos output (vt=1.7v) a3 o 88 74 dram address bit 3 4ma ttl compatible cmos output (vt=1.7v) a4 o 86 72 dram address bit 4 4ma ttl compatible cmos output (vt=1.7v) a5 o 85 71 dram address bit 5 4ma ttl compatible cmos output (vt=1.7v) a6 o 83 70 dram address bit 6 4ma ttl compatible cmos output (vt=1.7v) a7 o 81 69 dram address bit 7 4ma ttl compatible cmos output (vt=1.7v) a8 o 78 64 dram address bit 8 4ma ttl compatible cmos output (vt=1.7v) a9 o 76 63 dram address bit 9 4ma ttl compatible cmos output (vt=1.7v) a10 o 75 62 dram address bit 10 4ma ttl compatible cmos output (vt=1.7v) a11 o 73 61 dram address bit 11 4ma ttl compatible cmos io (vt=1.7v) dq0 i/o 68 57 dram data bit 0 4ma ttl compatible cmos io (vt=1.7v) dq1 i/o 69 58 dram data bit 1 4ma ttl compatible cmos io (vt=1.7v) dq2 i/o 70 59 dram data bit 2 4ma ttl compatible cmos io (vt=1.7v) dq3 i/o 72 60 dram data bit 3 4ma ttl compatible cmos io (vt=1.7v) ras# o 62 53 dram row address strobe 4ma ttl compatible cmos output (vt=1.7v) cas0# o 64 54 dram column address strobe 0 4ma ttl compatible cmos output (vt=1.7v) cas1# o 65 55 dram column address strobe 1 4ma ttl compatible cmos output (vt=1.7v) we# o 66 56 dram write enable 4ma ttl compatible cmos output (vt=1.7v) miscellaneous signal : 6 pins pin name type p-160 p-128 description characteristic definition xtali i 118 97 crystal or oscillator input (14.318m) crystal / oscilator input pad xtalo o 117 96 crystal output crystal output pad filt i/o 123 103 pll filter io pll filter io xclk o 120 98 internal pll clock output 2ma ttl compatible cmos output ring# i 127 106 ring detection input schmitt triggered cmos input (1.4v-2.2v) hook o 125 105 hook on output signal 2ma ttl compatible cmos output with tri-stste control(vt=1.7v) e 2 prom interface : 4 pins pin name type p-160 p-128 description characteristic definition romcs o 115 94 e 2 prom chip select 2ma ttl compatible cmos output with 50k w pull low
avance logic inc. ALS300 4 romclk o 111 91 e 2 prom clock 2ma ttl compatible cmos output (vt=1.7v) romdout i 114 93 e 2 prom serial data output ttl compatible cmos input (vt=1.7v) romdin o 112 92 e 2 prom serial data input 2ma ttl compatible cmos output (vt=1.7v) power/ground : 17 pins pin name type p-160 p-128 description characteristic definition vdd1 i 160 1 digital power 5v vdd2 i 21 19 digital power 5v vdd3 i 40 34 digital power 5v vdd4 i 60 52 digital power 5v vdd5 i 95 79 digital power 5v vdd6 i 108 89 digital power 5v vdd7 i 142 116 digital power 5v vdd8 i 121 101 digital power 5v avdd i 122 102 analog power 5v gnd1 i 1 5 digital ground gnd2 i 24 22 digital ground gnd3 i 41 38 digital ground gnd4 i 80 65 digital ground gnd5 i 98 81 digital ground gnd6 i 116 95 digital ground gnd7 i 144 118 digital ground agnd i 124 104 analog ground bonding option pin : 1 pin pin name type pin no description characteristic definition bond i * bonding option pin bond = 0 160 qfp 1 128 qfp part i : specification for sb core logic spec modified from als120 : 1. remove all recording command. 2. no support ide cdrom and modem 3. special mpu401 mode for internal wave engine. 4. remove analog block. (substitute analog block by ac97 codec) 5. all sb mixer write will generate an interrupt request via mxirq. 6. disable hardware power down pin. 7. add 128 bytes ram for special mpu401 output. 8. remove enhanced game-port. ALS300 power-on latch : on power up reset ,ALS300 latch the following pin state. their default state are : pin name default state midiout internal 50k w pull high romcs internal 50k w pull low after reset, pull high resistors will be disconnected from vcc and pull low resistor will disconnect from gnd. during the period of reset, the configur ation register cr3 will latch those input pin state. please refer to cr3 definition to get details. i/o register address: esp (enhanced sound processor): base+6h w esp-reset-port base+ah r esp-read-data base+ch w esp-command/data base+ch r esp-wr-status base+eh r esp-rd-status8 base+fh r esp-rd-status16 base = p 'n p logical device 0 port 60.1,0 and port 61.7-4;
avance logic inc. ALS300 5 baseenable = p 'n p logical device 0 port 30.0; esp-rd-status = esp-rd-status8 or esp-rd-status16 mixer & control: base+4h r/w mixer-index base+5h r/w mixer-data fm (opl3 compatible) synthesizer : base+0-3h r/w opl3/4 address:0-3 base+8,9h r/w opl3/4 address:0,1 adlibbase+0-3h r/w opl3/4 address:0-3 adlibbase = 0388h (p 'n p logical device 1) ; adlibenable = p 'n p logical device 1 port 30.0 (cr20.0); gameport : gamebase+0-7h r game-read gamebase+0-7h w game-write gamebase = 0200h (p 'n p logical device 2); gameenable = p 'n p logical device 2 port 30.0 (cr21.0); mpu401 and wave-table synthesizer: mpu401base+0h r midi input fifo mpu401base+0h w midi output fifo mpu401base+1h r midi-status mpu401base+1h w midi-command mpu401base+2h r/w ram-cnt mpu401base+3h r ram-data mpu401base = p 'n p logical device 3 port 60.1,0 (cr0c) and port 61.7-3 (cr0d); mpu401enable = p 'n p logical device 3 port 30.0 (cr0a); cr3.5 = 1: special mpu-401 or 0: standard mpu-401 mpu401base+2~3h is effective only when cr3.5=1. midiout : tri-state with internal pull up resisters when power up reset. 0 external 10k pull down 1 internal 50k pull up power up value cr3.5 power up latch value of midiout on power up reset , midiout will tri-state with 50k internal pull up resistors, after reset, these resistors will be disconnected from vcc. power management control register base+7h r/w power down register base+bh r/w power management register base+dh r activity status register
avance logic inc. ALS300 6 power management register: 8 bit read / write default ffh bit 7 fm clock select 1 : 14.318m or 14.318m/8 0 : 2m (from internal clock chip) bit 6 x reserved for future usage bit 5 0 power down opl3 bit 4 0 power down wave engine bit 3 x reserved bit 2 x reserved bit 1 0 power down mpu401 block bit 0 x reserved for future usage every bit of this register can read/write by pc and set to 1 by pc reset or by activity register specific bit is set to 1. wave engine is waked up by bit 4 of activity register any time. activity status register: read only default 00h bit 7,6 x reserved, read as 0 bit 5 1 opl3 is active bit 4 1 wave engine is active bit 3 x reserved, read as 0 bit 2 x reserved, read as 0 bit 1 1 mpu401 block is active bit 0 x reserved, read as 0 any read of this register will clear all bits to zero. each bit will be set when any of the following conditions happened: bit 5 = i/o access of opl3 register (chip select active) bit 4 = cr3.5 & bit 1 bit 1 = i/o access of mpu401 port + midiin input has ever been low power down register: read / write default a5h bit 7-0 software power down byte when write 5ah to this register, ALS300 will enter s/w power down mode until wake up by write with a5h. all other value will be ignored. game port definition: when i/o write to gameport, ALS300 will drive gd3, gd2, and gd1 low with 3-5ns time delay from each other. after system io write command goes inactive(siow_ goes high), ALS300 will sustain to drive low for extra 2us time period. at this time period, any read to gameport will force ALS300 to drive sd0-3 with 1 and sd7-4 with input data form gd7-gd4. after this time period, ALS300 will drive sd0-7 with input data from those pins when i/o read to gameport. ALS300 implement gd0 differently from gd1~3. it usually drive gd0 to low. when game-port write command is active, gd0 is tri-state until level on gd0 is high again. this implementation work fine with analog joystick and digital game pad.
avance logic inc. ALS300 7 sd7 gd7 sd6 gd6 sd5 gd5 sd4 gd4 sd3 invert of gd3 sd2 invert of gd2 sd1 invert of gd1 sd0 invert of gd0 gameport = gamebase+0-7h mpu401 mode definition : standard-mpu401 mode : (cr3.5=0) data a ccess is identical to mpu401. please refer to midi programming. special-mpu401 mode : (cr3.5=1) in this mode, any data write via mpu401 data port will store in ram and will not send out via midiout. read ram-data will fetch data from ram. when ram is not empty, ALS300 will generate an irq via mpu401 irq line. note that the ram is implemented as fifo. writing ram-cnt will acknowledge special mpu401 irq. ram-cnt r/w default : 80h bit 7 ram empty flag 0 non-empty 1 empty bit 6~0 ram write pointer write this register will acknowledge special mpu401 irq. ram-data read only bit 7~0 midi-data in special-mpu401 mode fm synthesizer : refer to als120 fm synthesizer specification esp register definition: esp-reset-port: write only bit 0 0 normal 1 reset esp bit 7..1 x reserved esp_reset should do the following things: a. reset esp to no operation status and clear esp busy flag. b. flush primary output fifo. c. reset any flag that may affect command execution. d. reset data latched by sb d/a to middle range. e. reset sample frequency to 44.1khz. f. reset dma block length to 0x7ff. esp-rd-status read only bit 7 0 no data on esp-read-data 1 data available at esp-read-data port bit 6..0 x reserved (same as esp-read-data bit 6..0)
avance logic inc. ALS300 8 read esp-rd-status8 will clear interrupt generated by the esp for non-bx type dma and midi. read esp-rd-status16 will clear interrupt for bx type dma . after cpu read the data from esp-read-data port, bit 7 of this read status port will reset to 0 (no data) until the next read data is available and bit 7 set to 1 (data available). esp-read-data read only bit 7..0 x the data return by esp esp-command/data write only bit 7..0 x the command or data to esp esp-wr-status: read only bit 7 0 esp is available for next command/data 1 esp is busy bit 6..0 x reserved (same as esp-read-data bit 6..0) after cpu write the command/data to the esp-c ommand/data port, bit 7 of this write s tatus will set to 1 (busy) until the esp processed the written command/data and waiting for the next command/data by reset bit 7 to 0 (not busy). any acknowledge byte must be readback before any new command is issued. esp will be set busy if any dma oper ation is started and will be set not busy if command port is read twice. interrupt acknowledge procedure : 1. io read(esp-rd-status8), clear non bx type dma irq 2. io read(esp-rd-status16), clear bx type dma irq . 3. io read(midi-data), clear mpu401 midi interrupt 4. write ram-cnt clear special-m idi type irq 5. no acknowledge is required for sb-mixer irq. mpu-401 midi register definition: midi-status read only bit 7 0 midi input data is available 1 no midi input bit 6 0 ready for midi data output or new midi command 1 midiout fifo full or midiout fifo not empty when midi_reset (if cr3.5=0) special mpu401 ram is full (if cr3.5=1) bit 5 midi ram status (effective in special midi mode) 0not full 1 full bit 5-0 reserved midi-c ommand write only bit 7..0 command to midi controller
avance logic inc. ALS300 9 in pass-thru mode, enter_uart 03fh return ack byte (0feh) in midi-data , generate an interrupt if switch to uart mode successfully. reading data port will clear the interrupt signal. midi_reset 0ffh return ack byte (0feh) in midi-data , generate an interrupt, stay in pass-thru mode. in uart mode, midi_reset 0ffh flush midiin fifo, wait until midiout fifo/midi ram empty, go to pass-thru mode . midi-data read/write read bit 7..0 midi data input in uart mode or acknowledge byte write bit 7..0 midi data output in uart mode ALS300 mixer register definition: mixer-index read/write bit 7 0 mixer 1 control bit 6..0 index mixer-data read/write bit 7..0 mixer or control data register by mixer-index mx00-mx7f mixer data register 00-7f base on mixer-index value cr00-cr3f control data register 00-3f base on mixer-index value with bit 7 and 6 = 1. sbconfign = mx80-mxbf write the following mixer register will generate a sb-mixer type irq to pci block : mx00, mx02, mx04, mx06, mx08, mx0a, mx0c, mx22 mx24, mx26, mx28, mx2e, mx30, mx31, mx32, mx33 mx34, mx35, mx36, mx37, mx38, mx39, mx3a, mx3b mx3c,mx3d,mx3e, mx3f, mx40, mx41, mx42, mx4c mx80, mx81, mxc6,mxc8 sound blaster pro: mx00 mixer reset write only any write to this port will reset mx00-mx7f to default value. esp_reset() does not affect any of the mixer register. mx02 master volume
avance logic inc. ALS300 10 ghost register write bit 7 x bit 6 x bit 5 x bit 4 x bit 3 mx30.7 & mx31.7 bit 2 mx30.6 & mx31.6 bit 1 mx30.5 & mx31.5 bit 0 mx30.4 & mx31.4 bit 3 mx30.3 bit 3 mx31.3 read bit 7 mx30.7 bit 6 mx30.6 bit 5 mx30.5 bit 4 mx30.4 bit 3 mx31.7 bit 2 mx31.6 bit 1 mx31.5 bit 0 mx31.4 bit 7..4 reserved bit 3..0 0 to 15, master volume left and right in 3 db step 0 -45 db (off) 15 0 db (maximum volume) mx04 digital audio left/right volume ghost register write bit 7 mx32.7 bit 6 mx32.6 bit 5 mx32.5 bit 4 mx32.4 bit 3 mx33.7 bit 2 mx33.6 bit 1 mx33.5 bit 0 mx33.4 bit 7 mx32.3 bit 3 mx33.3 read bit 7 mx32.7 bit 6 mx32.6 bit 5 mx32.5 bit 4 mx32.4 bit 3 mx33.7 bit 2 mx33.6 bit 1 mx33.5 bit 0 mx33.4 bit 7..4 0 to 15, digital audio left volume in 3 db step
avance logic inc. ALS300 11 bit 3..0 0 to 15, digital audio right volume in 3 db step 0 -45 db (off) 15 0 db (maximum volume) mx06 music volume ghost register write bit 7 x bit 6 x bit 5 x bit 4 x bit 3 mx34.7 & mx35.7 bit 2 mx34.6 & mx35.6 bit 1 mx34.5 & mx35.5 bit 0 mx34.4 & mx35.4 bit 3 mx34.3 bit 3 mx35.3 read bit 7 mx34.7 bit 6 mx34.6 bit 5 mx34.5 bit 4 mx34.4 bit 3 mx35.7 bit 2 mx35.6 bit 1 mx35.5 bit 0 mx35.4 bit 7..4 reserved bit 3..0 0 to 15, music volume left and right in 3 db step 0 -45 db (off) 15 0 db (maximum volume) mx08 cd-audio volume ghost register write bit 7 x bit 6 x bit 5 x bit 4 x bit 3 mx36.7 & mx37.7 bit 2 mx36.6 & mx37.6 bit 1 mx36.5 & mx37.5 bit 0 mx36.4 & mx37.4 bit 3 mx36.3 bit 3 mx37.3 read bit 7 mx36.7 bit 6 mx36.6 bit 5 mx36.5 bit 4 mx36.4
avance logic inc. ALS300 12 bit 3 mx37.7 bit 2 mx37.6 bit 1 mx37.5 bit 0 mx37.4 bit 7..4 reserved bit 3..0 0 to 15, cd-audio volume left and right in 3 db step 0 -45 db (off) 15 0 db (maximum volume) mx0a microphone volume ghost register write bit 7..3 x bit 2 mx3a.7 bit 1 mx3a.6 bit 0 mx3a.5 bit 2 mx3a.4 bit 1 mx3a.3 read bit 7..3 x bit 2 mx3a.7 bit 1 mx3a.6 bit 0 mx3a.5 bit 7..3 reserved bit 2..0 0 to 7, microphone volume in 6 db step 0 -42 db (off) 7 0 db (maximum volume) mx0c digital audio input control default 00h dummy read/write register bit 7,6 reserved bit 5 input filter enable bit 4 reserved bit 3 input filter high/low bit 2,1 input source bit 0 reserved input filter enable and input filter high/low are dummy read/write bits for sound blaster pro compatibility. input filter enable: 0 - input low-pass filter on, 1 - off input filter high/low: 0 - low filter (3.2 khz low pass), 1 - high filter (8.8 khz low pass) input source bit 2 bit 1 0 0 microphone (mx3d & mx3e = 1) 0 1 cd-audio (mx3d = 04h, mx3e = 02h) 1 0 microphone (mx3d & mx3e = 1)
avance logic inc. ALS300 13 1 1 external line-in (mx3d = 10h, mx3e = 08h) write to input source will update mx3d and mx3e input mixer left/right control register and 2 dummy bits. read from input source register will return 2 dummy bits. mx0e digital audio output control default 00h bit 7,6 reserved bit 5 output filter enable bit 4..2 reserved bit 1 stereo switch bit 0 reserved output filter enable is dummy read/write bit for sound blaster pro compatibility. output filter enable: 0 - output low-pass filter on, 1 - off stereo switch: 1 - stereo output, 0 - mono output stereo switch is not used in esp command bxh and cxh. mx22 master left/right volume ghost register write bit 7 mx30.7 bit 6 mx30.6 bit 5 mx30.5 bit 4 mx30.4 bit 3 mx31.7 bit 2 mx31.6 bit 1 mx31.5 bit 0 mx31.4 bit 7 mx30.3 bit 3 mx31.3 read bit 7 mx30.7 bit 6 mx30.6 bit 5 mx30.5 bit 4 mx30.4 bit 3 mx31.7 bit 2 mx31.6 bit 1 mx31.5 bit 0 mx31.4 bit 7..4 0 to 15, master left volume in 3 db step bit 3..0 0 to 15, master right volume in 3 db step 0 -45 db (off) 15 0 db (maximum volume) mx24 digital audio left/right volume same as mx04 mx26 music left/right volume
avance logic inc. ALS300 14 ghost register write bit 7 mx34.7 bit 6 mx34.6 bit 5 mx34.5 bit 4 mx34.4 bit 3 mx35.7 bit 2 mx35.6 bit 1 mx35.5 bit 0 mx35.4 bit 7 mx34.3 bit 3 mx35.3 read bit 7 mx34.7 bit 6 mx34.6 bit 5 mx34.5 bit 4 mx34.4 bit 3 mx35.7 bit 2 mx35.6 bit 1 mx35.5 bit 0 mx35.4 bit 7..4 0 to 15, music left volume in 3 db step bit 3..0 0 to 15, music right volume in 3 db step 0 -45 db (off) 15 0 db (maximum volume) mx28 cd-audio left/right volume ghost register write bit 7 mx36.7 bit 6 mx36.6 bit 5 mx36.5 bit 4 mx36.4 bit 3 mx37.7 bit 2 mx37.6 bit 1 mx37.5 bit 0 mx37.4 bit 7 mx36.3 bit 3 mx37.3 read bit 7 mx36.7 bit 6 mx36.6 bit 5 mx36.5 bit 4 mx36.4 bit 3 mx37.7 bit 2 mx37.6 bit 1 mx37.5 bit 0 mx37.4 bit 7..4 0 to 15, cd-audio left volume in 3 db step
avance logic inc. ALS300 15 bit 3..0 0 to 15, cd-audio right volume in 3 db step 0 -45 db (off) 15 0 db (maximum volume) mx2e external line left/right volume ghost register write bit 7 mx38.7 bit 6 mx38.6 bit 5 mx38.5 bit 4 mx38.4 bit 3 mx39.7 bit 2 mx39.6 bit 1 mx39.5 bit 0 mx39.4 bit 7 mx38.3 bit 3 mx39.3 read bit 7 mx38.7 bit 6 mx38.6 bit 5 mx38.5 bit 4 mx38.4 bit 3 mx39.7 bit 2 mx39.6 bit 1 mx39.5 bit 0 mx39.4 bit 7..4 0 to 15, external line left volume in 3 db step bit 3..0 0 to 15, external line right volume in 3 db step 0 -45 db (off) 15 0 db (maximum volume) sound blaster 16 (physical register): mx30 master left volume (dummy r/w) default 90h bit 7..3 0 to 31, master left volume in 1.5 db step bit 2..0 reserved 0 -46 db (off) 31 0 db (maximum volume) mx31 master right volume (dummy r/w) default 90h bit 7..3 0 to 31, master right volume in 1.5 db step bit 2..0 reserved 0 -46 db (off) 31 0 db (maximum volume) mx32 digital audio left volume (dummy r/w)
avance logic inc. ALS300 16 default 90h bit 7..3 0 to 31, digital audio left volume in 1.5 db step bit 2..0 reserved 0 -46 db (off) 31 0 db (maximum volume) mx33 digital audio right volume (dummy r/w) default 90h bit 7..3 0 to 31, digital audio right volume in 1.5 db step bit 2..0 reserved 0 -46 db (off) 31 0 db (maximum volume) mx34 music left volume (dummy r/w) default 90h bit 7..3 0 to 31, music left volume in 1.5 db step bit 2..0 reserved 0 -46 db (off) 31 0 db (maximum volume) mx35 music right volume (dummy r/w) default 90h bit 7..3 0 to 31, music right volume in 1.5 db step bit 2..0 reserved 0 -46 db (off) 31 0 db (maximum volume) mx36 cd-audio left volume (dummy r/w) default 00h bit 7..3 0 to 31, cd-audio left volume in 1.5 db step bit 2..0 reserved 0 -46 db (off) 31 0 db (maximum volume) mx37 cd-audio right volume (dummy r/w) default 00h bit 7..3 0 to 31, cd-audio right volume in 1.5 db step bit 2..0 reserved 0 -46 db (off) 31 0 db (maximum volume) mx38 external line left volume (dummy r/w) default 00h bit 7..3 0 to 31, external line left volume in 1.5 db step bit 2..0 reserved
avance logic inc. ALS300 17 0 -46 db (off) 31 0 db (maximum volume) mx39 external line right volume (dummy r/w) default 00h bit 7..3 0 to 31, external line right volume in 1.5 db step bit 2..0 reserved 0 -46 db (off) 31 0 db (maximum volume) mx3a microphone volume (dummy r/w) default 00h bit 7..3 0 to 31, microphone volume in 1.5 db step bit 2..0 reserved 0 -46 db (off) 31 0 db (maximum volume) mx3b pc speaker/mono input volume (dummy r/w) default 00h bit 7,6 0 to 3, mono input volume in 6 db step bit 5..0 reserved 0 -18 db (off) 3 0 db (maximum volume) mx3c output mixer control 1 (dummy r/w) default 1fh bit 7..5 reserved bit 4 external line left enable bit 3 external line right enable bit 2 cd-audio left enable bit 1 cd-audio right enable bit 0 microphone enable 0 mute 1 enable audio output mx3d input mixer left control (dummy r/w) default 15h bit 7 reserved bit 6 music left enable bit 5 dummy read/write bit bit 4 external line left enable bit 3 dummy read/write bit bit 2 cd-audio left enable bit 1 dummy read/write bit bit 0 microphone enable 0 mute 1 enable audio input
avance logic inc. ALS300 18 mx3e input mixer right control (dummy r/w) default 0bh bit 7 reserved bit 6 dummy read/write bit bit 5 music right enable bit 4 dummy read/write bit bit 3 external line right enable bit 2 dummy read/write bit bit 1 cd-audio right enable bit 0 microphone enable 0 mute 1 enable audio input mx3f input left mixer gain (dummy r/w) default 00h read/write bit 7,6 input left mixer gain control 00 no gain 01 2 x 10 4 x 11 4 x bit 5..0 reserved mx40 input right mixer gain (dummy r/w) default 00h read/write bit 7,6 input right mixer gain control 00 gain = 1 01 gain = 2 10 gain = 4 11 gain = 4 bit 5..0 reserved mx41 output left mixer gain (dummy r/w) default 00h bit 7,6 output left mixer gain 00 gain = 1 01 gain = 2 10 gain = 4 11 gain = 4 bit 5..0 reserved mx42 output right mixer gain (dummy r/w) default 00h bit 7,6 output right mixer gain 00 gain = 1 01 gain = 2 10 gain = 4 11 gain = 4 bit 5..0 reserved mx43 microphone automatic gain control (agc) (dummy r/w) default 00h dummy read/write register
avance logic inc. ALS300 19 bit 7..1 reserved bit 0 dummy read/write bit agc enable mx44 treble left control (dummy r/w) default 80h dummy read/write register bit 7..4 dummy read/write bit bit 3..0 reserved mx45 treble right control (dummy r/w) default 80h dummy read/write register bit 7..4 dummy read/write bit bit 3..0 reserved mx46 bass left control (dummy r/w) default 80h dummy read/write register bit 7..4 dummy read/write bit bit 3..0 reserved mx47 bass right control (dummy r/w) default 80h dummy read/write register bit 7..4 dummy read/write bit bit 3..0 reserved mx4c output mixer control 2 (dummy r/w) default 1fh bit 7~5 reserved bit 4 music left enable bit 3 music right enable bit 2 digital audio d/a left enable bit 1 digital audio d/a right enable bit 0 mono input enable 0 mute 1 enable audio into output mixer sound blaster 16 configuration register: mixer.80 sound blaster interrupt setup default 00h bit 7..5 reserved (read as 1) bit 4 irq11 bit 3 irq10 bit 2 irq7 bit 1 irq5 bit 0 irq9 0 : disable interrupt 1 : enable interrupt only 1 bit can be set at any time any write to pnp logical device 0 port 70h will set and reset corresponding bit in this register. write this register will generate sb-mixer irq except in pnp configuration state.
avance logic inc. ALS300 20 mixer.81 sound blaster dma setup 1 default 00h bit 7..4 reserved, read as 0 bit 3 dma3 for sb dma co mmand bit 2 reserved, read as 0 bit 1 dma1 for sb dma co mmand bit 0 dma0 for sb dma co mmand 0: disable dma 1: enable dma any write to pnp logical device 0 port 74h will set one of this register bit3-0 as 1. write this register will generate sb-mixer irq except in pnp configuration state. mixer.82 interrupt status read only default 00h bit 7~4 reserved bit 3 special mpu401 interrupt request bit 2 mpu-401 midi interrupt request bit 1 bx type command dma interrupt request bit 0 non-bx type command dma interrupt request 0 : no interrupt 1 : interrupt triggered bit 0,1 always use sb irq line, bit 2 can share sb irq line only when mpu401 irq line is programmed to be the same as sb irq line by pnp manager. normally bit 2 use mpu401 irq line. mixer.8d ALS300 backward compatible register default 03h (version f or latter default = 07h) read/write bit 7..3 reserved,read as 0 bit 2 continuous dma oper ation mode 0 irq controlled continuous dma mode. 1 fifo controlled continuous dma mode. bit1,0 reserved(read as 1) mx8d.2 is the ghost bit of cr0.1. control register definition : cr0 sound blaster configuration default 00h (version f or latter default = 06h) read/write bit 7..6 reserved, read as 0 bit 5 reserved, read as 0 bit 4 dma block enable for sb dma co mmand bit 3 dma block request size bit 2 dma mode control for 90h co mmand bit 1 continuous dma mode control bit 0 reserved
avance logic inc. ALS300 21 bit 4: 0 single cycle dma request 1 block cycle dma request bit 3: 0 block cycle dma requset when pcm fifo is not full : playback not empty: record 1 dma requset when pcm fifo is less then half full during playback or less then half empty during recording bit 2 0 irq controlled 90h command (sb16 version) 1 fifo controlled 90h command (sbpro version) bit 1 0 irq controled continuous dma mode 1 fifo controlled continuous dma mode cr2 misc.control default 00h read/write bit 7 reserved bit 6 reserved bit 5 reserved bit 4 read as 1 bit 3 reserved, read as 0 bit 2 reserved bit 1 reserved, read as 0 bit 0 reserved,(read as 0) cr3 configuration default 23h bit 7-2 read/write bit 1-0 read only bit 6 read only bit 7 reserved bit 6 e 2 prom control (read only) bit 5 internal/external mpu401 midi output select bit 4 reserved bit 3 reserved bit 2 reserved bit 1,0 chip version number ( read as 11 ) bit 1 bit 0 0 0 als007sp 01als100 1 0 als007/wta2000 1 1 als200/als110//als120/ALS300 power up input value midiout,romcs is tri-state with internal 50k pull low resisters when power up reset. midiout 0 external 10k pull down
avance logic inc. ALS300 22 1 internal pull up romcs 0 external 10k pull up 1 internal pull down power up latched value cr3.6 !romcs cr3.5 midiout cr3.6 0 e 2 prom is disabled 1e 2 prom is enabled (default) cr3.5 0 external wave blaster midi (standard-mpu401) 1 internal wave engine midi (special-mpu401) cr4 (for testing) same as pnp0-60 cr5 (for testing ) same as pnp0-61 cr6 same as pnp0-70 cr7 same as pnp1-60 cr8 same as pnp0-74 cra same as pnp3-30 crb same as pnp1-61 crc same as pnp3-60 crd same as pnp3-61 cre same as pnp3-70 crf same as pnp2-60 cr11 same as pnp2-61 cr17 fifo status default 00h bit 7-3 read only bit 2-0 read/write bit 7 reserved bit 6 reserved bit 5 1 primary pcm fifo underrun flag bit 4 1 midi output fifo full flag bit 3 1 midi input fifo overrun flag bit 2 1 flush midi in and out fifo bit 1 1 flush primary pcm fifo bit 0 1 active xrst_ to reset internal opl3 any time during dma playback by pr imary fifo, if the fifo is empty when new sample is needed, bit 5 will be set. any time midi output fifo is full, bit 4 will be set. any time a new midi input data is r eceived and the midi input fifo is full, bit 3 w ill be set. reading this register will clear all flags(ie. bit 7-3). bit 2-0 are sticky, that is, hardware will not clear them automatically and it is need for software to clear the bits.
avance logic inc. ALS300 23 cr18 esp major version number read/write default 04h cr19 esp minor version number read/write default 02h cr1a mpu401 midi uart mode control cr1a.7-5 r/w cr1a.4-0 r default 0xh bit 7 0 internal midiin from external midiin pad 1 internal midiin from internal midiout bit 6 0 internal midiout to external midiout pad 1 external midiin pad to external midiout pad bit 5 0 regular midi clock 1 fast midi clock(14.318mhz) bit 4 x reserved bit 3 0 mpu401 midi at pass-thru mode 1 mpu401 midi at uart mode bit 2 x reserved bit 1 x reserved bit 0 x reserved when midi is in pass-thru mode, midi clock is stopped. internal midiin is tied high and external midiout is connected to external midiin pad. in mpu-401 uart mode, the internal midiin input, the external midiout output and the midi clock are controlled by cr1a.7-5 bits. in midi loop back mode, when midiin fifo is full, midi clock will be stop until midiin is not full. this will aviod midi fifo overrun. special m idi mode dont support loop-back function even midi is configured as loop-back mode. cr20 same as pnp1-30 cr21 same as pnp2-30 cr3a misc control register default 20h bit 7 joystick/game-pad select 0 joystick mode (analog game-port) 1 game-pad mode (digital game-port) bit 6~4 gd0 floating period select 000 300us
avance logic inc. ALS300 24 001 400us ? 110 900us 111 1000us bit 3 reserved bit 2 fifo crc check control 0normal 1 clear crc-32 shift register contents. bit 1 reserved bit 0 0 disable sb16 e3 command 1 enable sb16 e3 command when cr3a.7=1(game-pad mode), ALS300 will drive gd0 to low. when sw write port 201h, ALS300 will release it for a period defined in cr3a.6~4 and drive it to low again until next io write 201h. for other operation, digital game-port is identical to analog game-port. cr3b crc-32 byte 0 default : 00h bit 7~0 crc-32 bit 7~0 cr3c crc-32 byte 1 default : 00h bit 7~0 crc-32 bit 15~8 cr3d crc-32 byte 2 default : 00h bit 7~0 crc-32 bit 23~16 cr3e crc-32 byte 3 default : 00h bit 7~0 crc-32 bit 31~24 cr3f scrach 8 bit read/write register default 00h bit 7..0 x dummy read/write bit for s/w switch plug and play register: pnpy-xx device y pnp index xx register pnpxx card level pnp index xx register sound blaster configuration pnp0-30 default :00h device control bit type function 7:1 reserved , read as 0 0 r/w device 0 control, 0 : disable 1 : enable pnp0-31 default : 00h io check control bit type function 7:2 reserved , read as 0 1 r/w io range check control, 0 : disable 1 : enable 0 r/w io range check return data 0 : 0xaa 1 : 0x55 pnp0-60 default : 00h device 0 base address high byte bit type function 7:2 reserved , read as 0 1:0 r/w sbbase[9..8] pnp0-61 default : 00h device 0 base address low byte bit type function 7:4 r/w sbbase[7..4] 3:0 reserved, read as 0
avance logic inc. ALS300 25 pnp0-70 default : 00h device 0 irq select bit type function 7:4 reserved , read as 0 3:0 r/w sb irq pnp0-71 default : 02h device 0 irq type bit type function 7:0 r read as 02h pnp0-74 default : 04h device 0 dma select 1 bit type function 7:3 reserved , read as 0 2:0 r/w sb dma channel adlib configuration pnp1-30 default : 00h device control bit type function 7:1 reserved , read as 0 0 r/w device 1 control, 0 : disable 1 : enable pnp1-31 default : 00h io check control bit type function 7:2 reserved , read as 0 1 r/w io range check control, 0 : disable 1 : enable 0 r/w io range check return data 0 : 0xaa 1 : 0x55 pnp1-60 default : 03h device 1 base address high byte bit type function 7:3 r read as 0 2:0 r/w adlibbase[10..8] pnp1-61 default : 88h device 1 base address low byte bit type function 7:3 r/w adlibbase[7..3] 2:0 reserved game port configuration pnp2-30 default : 00h device control bit type function 7:1 reserved , read as 0 0 r/w device 1 control, 0 : disable 1 : enable pnp2-31 default : 00h io check control bit type function 7:2 reserved , read as 0 1 r/w io range check control, 0 : disable 1 : enable 0 r/w io range check return data 0 : 0xaa 1 : 0x55 pnp2-60 default : 02h device 2 base address high byte bit type function 7:3 r read as 0 2:0 r/w gamebase[10..8] pnp2-61 default : 00h device 2 base address low byte bit type function 7:3 r/w gamebase[7..3] 2:0 r read as 0 mpu401 configuration pnp3-30 default : 00h device control bit type function
avance logic inc. ALS300 26 7:1 reserved , read as 0 0 r/w device 1 control, 0 : disable 1 : enable pnp3-31 default : 00h io check control bit type function 7:2 reserved , read as 0 1 r/w io range check control, 0 : disable 1 : enable 0 r/w io range check return data 0 : 0xaa 1 : 0x55 pnp3-60 default : 00h device 3 base address high byte bit type function 7:2 reserved, read as 0 1:0 r/w mpubase[9..8] pnp3-61 default : 00h device 3 base address low byte bit type function 7:4 r/w mpubase[7..4] 3:0 reserved, read as 0 pnp3-70 default : 00h device 3 irq select bit type function 7:4 reserved , read as 0 3:0 r/w mpu401 irq pnp3-71 default : 02h device 3 irq type bit type function 7:0 r read as 02h all other plug and play registers not specified are read only as 0 except 74h,75h which should return 04h. crc-32 for fifo check : ALS300 build-in crc-32 check circuit for speed up testing. it can help verification in development stage. to start crc check, toggle cr3a.2 1 time. the clock of crc-32 shift register is the clock of sb primary fifo. when cpu read cr3b~3e,ALS300 return crc-32 shift register content to cpu. external serial e 2 prom access: external serial e 2 prom is enabled when cr3.6 = 1. ALS300 only supports ns9346 series (or compatible clone unit) serial e 2 prom which has the following physical storage organization: 64 x 16 (1024 bits, 64 storage c ell, each 16 bits wide, little endian ) if the external serial e 2 prom is enabled, als 300will read the following data from external e 2 prom when als120 is reset (h/w res et). pci subsystem vendor id byte 0-1 pci subsystem id byte 2-3 pnp header byte 4-12 pnp version byte 13-15 identifier string byte 16-59 resource checksum 00 byte 60 (cr3.4=0,cr3.3=0) the orignal pnp header,identifier string and resource checksum will be updated by the above data. their default value are listed in plug and play header/resource data. ALS300 will not read e 2 prom except ALS300 is reset again. after reading pci subsystem vendor id/subsystem id (byte 0~3), ALS300 sb logic send these data to ALS300 pci interface. test mode access: access gcr90 will enter the test mode you set. power management: try the best power management for both active and inactive stage of ALS300 for note book applic ation.
avance logic inc. ALS300 27 pay special attention to data bus and address bus inside ALS300 because this may be the very heavy power consumption source. use internal block chip select signal to be the block power control signal as much as possible. the pull up resistors on any power up configuration pin must be disconnected from vcc after reset. h/w power-down pin is disabled. s/w power down mode is the same as h/w power down mode except rst and i/o access to power down register are still enable. the i/o access of the following register does not need power management control and must have real time response. power down register fifo control attention: whenever new continuous dma co mmand for 8/16 bit wave playback is r eceived, sb16 esp should always flush primary pcm fifo. ALS300 should has a primary fifo r/w counter reset indicator, isa reset or esp reset should reset this indicator. when current dma oper ation is 8 bit stereo or 16 bit mono, if dma transfer times is not even, this indicator should indicate bit 0 of fifo r/w counter must be reset by esp when new dma command is r eceived. when current dma oper ation is 16 bit stereo, if dma transfer times is not multiple times of 4, this indicator should indicate that bit 0 and bit 1 of fifo r/w counter must be reset by esp when new dma co mmand is r eceived. any time when new dma co mmand is r eceived, this indicator must be reset after pr imary fifo r/w counter control. midiout fifo size : 16 bytes midiin fifo size : 8 bytes midiout ram s ize : 128 bytes
avance logic inc. ALS300 28 appendix a : ALS300 pnp resource data ALS300 plug and play definition: plug and play function block can be enabled by either the standard isa plug and play initial key sequence or our self-defined initial key sequence. please refer to the isa plug and play spec 1.0 to get the standard initial key sequence. our self-defined initial key sequence is as follows: 95,ca,e5,f2, f9,fc,7e,bf, 5f,2f, 17,0b, 05, 82,c1,e0, 70, 38,1c,0e, 87, 43, 21,90, 48, 24,12 ,89, c4, 62, b1,d8 plug and play head er/resource data: 200 byte rom ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; plug and play header ; 9 bytes ram ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; db 0x05,0x93 ; vendor id "als" db 0x03,0x00 ; chip id "300" db 0xff,0xff,0xff,0xff ; serial number ffffffff db 0x99 ; lfsr checksum ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; plug and play resource data ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; db 0x0a ; plug and play version number db 0x10 ; version 1.0 db 0x00 ; ALS300 version 0.0 db 0x82 ; ansi identifier string db 0x29,0x00 ; string length db 0x50,0x6e,0x50,0x20 db 0x53,0x6f,0x75,0x6e db 0x64,0x20,0x43,0x68 db 0x69,0x70,0x20,0x20 db 0x20,0x20,0x20,0x20 db 0x20,0x20,0x20,0x20 db 0x20,0x20,0x20,0x20 db 0x20,0x20,0x20,0x20 db 0x20,0x20,0x20,0x20 db 0x20,0x20,0x20,0x20,0x20 ;pnp sound chip ; ; logical device 0 ; sound blaster resource ; db 0x15 ; logical device id db 0x00,0x00 ; device id 0-sound blaster base db 0x00,0x03 ; ALS300 db 0x02 ; support i/o range check ; db 0x31,0x00 ; best case default db 0x47,0x01 ; i/o port select, 16 bit i/o address decode db 0x20,0x02 ; min. i/o base 0x0220
avance logic inc. ALS300 29 db 0x20,0x02 ; max. i/o base 0x0220 db 0x10 ; i/o align every 16 byte db 0x10 ; i/o length 16 byte db 0x22 ; irq format, high edge triggered db 0x20,0x00 ; irq 5 db 0x2a ; dma format 0 db 0x02 ; dma channel 1 db 0x68 ; 8 bit dma type f, byte count db 0x31,0x01 ; average case db 0x47,0x01 ; i/o port select,16 bit i/o address decode db 0x20,0x02 ; min. i/o base 0x0220 db 0x80,0x02 ; max. i/o base 0x0280 db 0x20 ; i/o align every 32 byte db 0x10 ; i/o length 16 byte db 0x22 ; irq format, high edge triggered db 0xa0 ; irq 5,7 db 0x0e ; irq 9,10,11 db 0x2a ; dma format 0 db 0x0b ; dma channel 0,1 or 3 db 0x68 ; 8 bit dma type f, byte count db 0x31,0x02 ; worst case db 0x47,0x01 ; i/o port select,16 bit i/o address decode db 0x00,0x01 ; min. i/o base 0x0100 db 0xf0,0x03 ; max. i/o base 0x03f0 db 0x10 ; i/o align every 16 byte db 0x10 ; i/o length 16 byte db 0x22 ; irq format,high edge triggered db 0xa0 ; irq 5,7 db 0x0e ; irq 9,10,11 db 0x2a ; dma format 0 db 0x0b ; dma channel 0,1 or 3 db 0x68 ; 8 bit dma type f, byte count db 0x38 ; end of cases ; ; logical device 1 ; adlib resource ; db 0x15 ; logical device id db 0x01,0x00 ; device id 1-adlib db 0x00,0x03 ; ALS300 db 0x02 ; support i/o range check ; ; when i/o range check enable, ALS300 will not enable any ; kind of internal or external fm chip select signal . ; ALS300 will drive sd0-7 as 0x55 or 0xaa as defined by the spec. ; db 0x31,0x00 ; best case db 0x47,0x01 ; i/o port select,16 bit i/o address decode db 0x88,0x03 ; min. i/o base 0x0388 db 0x88,0x03 ; max. i/o base 0x0388 db 0x08 ; i/o align every 8 byte db 0x04 ; i/o length 4 byte ; db 0x31,0x01 ; worst case (1997,5,13) db 0x47,0x01 ; i/o port select,16 bit i/o address decode db 0x00,0x03 ; min. i/o base 0x0300 (1997,5,13)
avance logic inc. ALS300 30 db 0xff,0x07 ; max. i/o base 0x07ff (1997,5,13) db 0x08 ; i/o align every 8 byte (1997,6,12) db 0x04 ; i/o length 4 byte (1997,5,13) ; db 0x38 ; end case (1997,5,13) ; ; logical device 2 ; game port ; db 0x15 ; logical device id db 0x02,0x00 ; device id 2-game port db 0x00,0x03 ; ALS300 db 0x02 ; support i/o range check ; ; when i/o range check enable, ALS300 will not enable normal ; or enhanced mode gameport read and write. ; ALS300 will drive sd0-7 as 0x55 or 0xaa as defined by the spec. ; db 0x31,0x00 ; best case db 0x47,0x01 ; i/o port select,16 bit i/o address decode db 0x00,0x02 ; min. i/o base 0x0200 db 0x00,0x02 ; max. i/o base 0x0200 db 0x08 ; i/o align every 8 byte db 0x08 ; i/o length 8 byte ; db 0x31,0x01 ; worst case (1997,5,13) db 0x47,0x01 ; i/o port select,16 bit i/o address decode db 0x00,0x02 ; min. i/o base 0x0200 db 0xff,0x07 ; max. i/o base 0x07ff db 0x08 ; i/o align every 8 byte db 0x08 ; i/o length 8 byte ; db 0x38 ; end case (1997,5,13) ; ; logical device 3 ; mpu401 midi resource ; db 0x15 ; logical device id db 0x03,0x00 ; device id 3-mpu401 midi db 0x00,0x03 ; ALS300 db 0x02 ; support i/o range check ; db 0x31,0x00 ; best case default db 0x47,0x01 ; i/o port select, 16 bit i/o address decode db 0x30,0x03 ; min. i/o base 0x0330 db 0x30,0x03 ; max. i/o base 0x0330 db 0x10 ; i/o align every 16 byte db 0x04 ; i/o length 4 byte db 0x22 ; irq format, high edge triggered db 0x00,0x02 ; irq 9 ; db 0x31,0x01 ; average case db 0x47,0x01 ; i/o port select,16 bit i/o address decode db 0x00,0x01 ; min. i/o base 0x0100 db 0xf0,0x03 ; max. i/o base 0x03f0 db 0x10 ; i/o align every 16 byte db 0x04 ; i/o length 4 byte db 0x22 ; irq format, high edge triggered
avance logic inc. ALS300 31 db 0xa0 ; irq 5, 7 db 0x0e ; irq 9, 10, 11 ; db 0x38 ; end of cases ; ;end of resource data db 0x79 ; end tag ;************************** ; checksum ;******************** db 1d ; check sum
avance logic inc. ALS300 32 appendix b : esp command set ALS300 only support playback and its related command. * undocumented $ sound blaster pro only # sound blaster 16 only 0xh reserved 1xh set audio output mode for 4:1 adpcm 2 to 8 bit playback 3xh reserved 4xh set sample rate and continuos/special dma block length 5xh reserved 6xh reserved 7xh set audio output for all adpcm, 8 bit playback 8xh output silence 9xh 8 bit special dma mode playback/record axh set mono/stereo input mode bxh 16 bit dma audio i/o cxh 8 bit dma audio i/o dxh control dma and speaker exh esp version and diagnostic test fxh test irq and esp rom all 8-bit esp command is unsigned pcm except cxh command. all 8-bit esp command is mono except co mmand 14h,1ch,9xh and cxh 8 bit and 4:1 adpcm 2 to 8 bit output 1xh bit 3 0 direct/normal dma mode 1 continuous dma mode bit 2 0 direct mode 1 dma mode bit 1 0 8 bit data 1 4:1 adpcm 2 to 8 bit mode bit 0 0 normal 1 the first adpcm block with reference byte 10h 8 bit direct mode output a. esp_write(10h) b. esp_write(single-sample) c. wait for next sample time, go to a. 14h 8 bit normal dma output a. esp_write(14h) b. esp_write(length.low) c. esp_write(lenght.high) length = # of byte transfer - 1 esp will generate an interrupt after the specified size of data transferred.
avance logic inc. ALS300 33 16h 4:1 adpcm 2 to 8 bit nor mal dma output a. esp_write(16h) b. esp_write(length.low) c. esp_write(length.high) length = # of byte transfer - 1 esp will generate an interrupt after the specified size of data transferred. 17h first 4:1 adpcm 2 to 8 bit nor mal dma output a. esp_write(17h) b. esp_write(length.low) c. esp_write(length.high) length = # of byte transfer - 1 esp will generate an interrupt after the specified size of data transferred. 1ch 8 bit continuous dma output esp_write(1ch) esp will generate an interrupt for every specified block size transferred. 1eh 4:1 adpcm 2 to 8 bit continuous dma output esp_write(1eh) esp will generate an interrupt for every specified block size transferred. 1fh first 4:1 adpcm 2 to 8 bit continuous dma output esp_write(1fh) esp will generate an interrupt for every specified block size transferred. set sample rate and continuous/sp ecial dma block length 4xh 40h set sample rate time constant time constant = 256d - (1,000,000d / ( channel * sampling rate)) channel = 1 for mono or bx,cx type command, 2 for stereo a. esp_write(40h) b. esp_write(time constant) #41h set playback sample rate a. esp_write(41h) b. esp_write(frequency.high) c. esp_write(frequency.low) sampling frequency = 4 khz to 48 khz, either mono or stereo
avance logic inc. ALS300 34 48h set block length for continuous and special dma a. eps_write(48h) b. esp_write(length.low) c. esp_write(length.high) length = # of byte transfer - 1 esp will generate an interrupt after transferred the block of data. after reset, the default block size is 2048. length = 07ffh all adpcm 8 bit output 7xh bit 3 0 normal dma mode 1 continuous dma mode bit 2 bit 1 0 0 reserved 0 1 4:1 adpcm 2 to 8 bit mode 1 0 2:1 adpcm 4 to 8 bit mode 1 1 3:1 adpcm 2.6 to 8 bit mode bit 0 0 normal 1 the first adpcm block with reference byte *72h 4:1 adpcm 2 to 8 bit nor mal dma output a. esp_write(72h) b. esp_write(length.low) c. esp_write(length.high) length = # of byte transfer - 1 esp will generate an interrupt after the specified size of data transferred. *73h first 4:1 adpcm 2 to 8 bit nor mal dma output a. esp_write(73h) b. esp_write(length.low) c. esp_write(length.high) length = # of byte transfer - 1 esp will generate an interrupt after the specified size of data transferred. 74h 2:1 adpcm 4 to 8 bit nor mal dma output a. esp_write(74h) b. esp_write(length.low) c. esp_write(length.high) length = # of byte transfer - 1 esp will generate an interrupt after the specified size of data transferred.
avance logic inc. ALS300 35 75h first 2:1 adpcm 4 to 8 bit nor mal dma output a. esp_write(75h) b. esp_write(length.low) c. esp_write(length.high) length = # of byte transfer - 1 esp will generate an interrupt after the specified size of data transferred. 76h 3:1 adpcm 2.6 to 8 bit nor mal dma output a. esp_write(76h) b. esp_write(length.low) c. esp_write(length.high) length = # of byte transfer - 1 esp will generate an interrupt after the specified size of data transferred. 77h first 3:1 adpcm 2.6 to 8 bit nor mal dma output a. esp_write(77h) b. esp_write(length.low) c. esp_write(length.high) length = # of byte transfer - 1 esp will generate an interrupt after the specified size of data transferred. *7ah 4:1 adpcm 2 to 8 bit continuous dma output esp_write(7ah) esp will generate an interrupt for every specified block size transferred. *7bh first 4:1 adpcm 2 to 8 bit continuous dma output esp_write(7bh) esp will generate an interrupt for every specified block size transferred. 7ch 2:1 adpcm 4 to 8 bit continuous dma output esp_write(7ch) esp will generate an interrupt for every specified block size transferred. 7dh first 2:1 adpcm 4 to 8 bit continuous dma output esp_write(7dh) esp will generate an interrupt for every specified block size transferred. 7eh 3:1 adpcm 2.6 to 8 bit continuous dma output esp_write(7eh)
avance logic inc. ALS300 36 esp will generate an interrupt for every specified block size transferred. 7fh first 3:1 adpcm 2.6 to 8 bit continuous dma output esp_write(7fh) esp will generate an interrupt for every specified block size transferred. output silence 8xh bit 3..0 x reserved 80h silence audio for a duration a. esp_write(80h) b. esp_write(duration.low) c. esp_write(duration.high) duration = # of silence sample period - 1 after the specified duration elapses, esp will generate an interrupt. during silence period, esp out 0x80 to pcm d/a. 8 bit special dma playback/record 9xh all special dma mode use co mmand 48h to set the transfer block size. the non-continuous special dma mode w ill interrupt the cpu at the end of the transfer block and wait for new command. use reset-esp() to end the continuous special dma, all other parameters remains the same after reset-esp( ). special dma playback: mono mx0e.1 = 0 stereo mx0e.1 = 1 default mono after isa reset or mixer reset default mono after isa reset or esp reset bit 3 1 audio input bit 3 0 audio output bit 2 x reserved bit 1 x reserved bit 0 0 continuous dma bit 0 1 non-continuous dma $90h 8 bit continuous special dma output esp_write(90h) esp will generate an interrupt for every specified block size transferred. ALS300 use cr0.2 to control the dma running mode of 90h command. when cr0.2 is 1, esp will continue dma transfer no matter whether the interrupt is acknowledged, this is sbpro 90
avance logic inc. ALS300 37 command. when cr0.2 is 0, esp will continue dma transfer after the interrupt is acknowledged, this is sb16 90h command. $91h 8 bit non-continuous special dma output esp_write(91h) esp will generate an interrupt after the specified size of data transferred. for non-continuous special dma output, every time when esp receives the 91h command, esp will use the block length that most recently set by command 48h to begin the special dma transfer. so if every block of dma data is the same size, software needs only set block length one time by using command 48h. when each block is transfered over, software needs only send 91h command to esp, the dma transfer will then continue with previous block length. 16 bit dma audio i/o #bxh bit 3 0 audio output (bit 3 should be 0 in ALS300) 1 audio input bit 2 0 non-continuous dma 1 continuous dma bit 1 x reserved bit 0 x reserved fifo will reset when esp r eceives any dig ital audio i/o command. fifo is always on. a. esp_write(bxh) b. esp_write(mode) c. esp_write(length.low) d. esp_write(length.high) mode bit 7 x reserved bit 6 x reserved bit 5 0 mono 1stereo bit 4 0 unsigned (0--8000h--ffffh) 1 signed (8000h--0--7fffh) bit 3 x reserved bit 2 x reserved bit 1 x reserved bit 0 x reserved length = # of 16 bit sample -1 esp will generate an interrupt after the specified size of data transferred (if non-continuous) or every block(if continuous). 8 bit dma audio i/o #cxh bit 3 0 audio output (bit 3 should be 0 in ALS300) 1 audio input bit 2 0 non-continuous dma 1 continuous dma bit 1 x reserved
avance logic inc. ALS300 38 bit 0 x reserved fifo will reset when esp r eceives any dig ital audio i/o command. fifo is always on. a. esp_write(cxh) b. esp_write(mode) c. esp_write(length.low) d. esp_write(length.high) mode bit 7 x reserved bit 6 x reserved bit 5 0 mono 1stereo bit 4 0 unsigned (0--80h--ffh) 1 signed (80h--0--7fh) bit 3 x reserved bit 2 x reserved bit 1 x reserved bit 0 x reserved length = # of 8 bit sample -1 esp will generate an interrupt after the specified size of data transferred (if non-continuous) or every block(if continuous). control dma and digital audio dxh d0h pause non bx type dma transfer esp_write(d0h) the dma request is stopped after this co mmand. internal fifo will continue until the fifo is empty (playback) or full (record). the dma request w ill resume after command d4h or any of new dma command is issued. d1h turn digital audio on esp_write(d1h) set digital audio status flag for d8h command. d3h turn digital audio off esp_write(d3h) reset digital audio status flag for d8h command. audio status flag is reset after system reset or esp_reset(). d4h resume non bx type dma transfer esp_write(d4h) the dma request that is suspended by the co mmand d0h is enable again. the internal fifo is working as usual in pause or resume dma mode.
avance logic inc. ALS300 39 #d5h pause bx type dma mode transfer esp_write(d5h) the dma request is stopped after this co mmand. internal fifo will continue until the fifo is empty (playback) or full (record). the dma request w ill resume after command d6h or any of new dma command is issued #d6h resume bx type dma mode transfer esp_write(d6h) the dma request that is suspended by the co mmand d5h is enable again. the internal fifo is working as usual in pause or resume dma mode. this co mmand is no use to non-bx type command dma transfer. d8h get digital audio status a. esp_write(d8h) b. esp_read(status) c. status = 00h (digital audio off) or ffh (digital audio on) #d9h exit current bx type continuous dma transfer esp_write(d9h) causes the esp to finish the current block, then cease transferring. use this command while the dma is transferring the last block of audio data from/to esp. esp-reset() or any of new dma co mmand should reset this flag. dah exit current non-bx type continuous dma transfer esp_write(dah) causes the esp to finish the current block, then cease transferring. use this command while the dma is transferring the last block of audio data from/to esp. esp-reset() or any of new dma co mmand should reset this flag. esp version and diagnostic exh *e0h read/write diagnostic test a. esp_write(e0h) b. esp_write(test-data) c. esp_read(result) d. if result = bit invert of test-data, esp is working e1h get esp version number a. esp_write(e1h) b. esp_read(major.version) c. esp_read(minor.version) sound blaster pro default version 3.02 sound blaster 16 default version 4.02 ALS300 default 4.02
avance logic inc. ALS300 40 major version = cr18 minor version = cr19 *e2 dma testing computes the subroutines starting address for digital sound playback or recording according to the dedicated algorithm. sends back the result to system via dma method(two bytes transfered). a. esp_write(e2h) b. esp_write(first byte b1),return r1 via dma c. esp_write(e2h) d. esp_write(second byte b2),return r2 via dma formula for r1: r1 = ( b1.7..5 + 1 ) * 0x40 + b1.3 * 0x10 + b1.0 * 0x02 - b1 (this is 8 bit unsigned operation) formula for r2: 1. r2_h = 0xe0 + b2.4 * 0x20 - b2.6 * 0x80 2. r2_h = r2_h + b1 & 0xe0 - b2 & 0xf0 3. r2_l = 0x05 + b2.1 * 0x04 - b2 & 0x0f 4. r2 = r2_h & 0xf0 + r2_l & 0x0f + b1.0 * 0x01 - b1 & 0x1e 5. r2 = r2 + b1.3 * 0x10 (this is 8 bit unsigned operation) *e3 copyright message a. esp_write(e3h) b. esp_read(message) message : text "copyright (c) creative technology ltd, 1992.",0h) hex 43 4f 50 59 52 49 47 48 54 20 28 43 29 20 43 52 45 41 54 49 56 45 20 54 45 43 48 4e 4f 4c 4f 47 59 20 4c 54 44 2c 20 31 39 39 32 2e 00 this command is valid only when cr3a.0 = 1. *e4 send test byte for command e8h a. esp_write(e4h) b. esp_write(test-data) *e8 read diagnostic byte a. esp_write(e4h) b. esp_write(test-data) c. esp_write (e8h) c. esp_read(result) d. if result = test-data, esp is working testing fxh *f2h generate an interrupt for test esp_write(f2h) esp will generate an interrupt immediately after this command.
avance logic inc. ALS300 41 *f8 read back dedicated byte 00 a. esp_write(f8h) b. esp_read(result) c. if result = 00,esp is working
avance logic inc. ALS300 42 appendix c : pcm data format digitized sound data format and order: length format min value mid value max value 8 bit unsigned 00h 80h ffh 8 bit signed 80h 00h 7fh 16 bit unsigned 0000h 8000h ffffh 16 bit signed 8000h 0000h 7fffh pcm sample order: z 8 bit mono byte no. n n+1 n+2 n+3 n+4 sample pcm 0 pcm 1 pcm 2 pcm 3 pcm 4 z 8 bit stereo with 1xh and 9xh type command byte no. 2n 2n+1 2n+2 2n+3 2n+4 sample pcm0.r pcm0.l pcm1.r pcm1.l pcm2.r z 8 bit stereo with cxh type command byte no. 2n 2n+1 2n+2 2n+3 2n+4 sample pcm0.l pcm0.r pcm1.l pcm1.r pcm2.l z 16 bit mono byte no. 2n 2n+1 2n+2 2n+3 2n+4 sample pcm0.low pcm0.high pcm1.low pcm1.high pcm2.low z 16 bit stereo byte no. 4n 4n+1 4n+2 4n+3 4n+4 sample pcm0.l.low pcm0.l.high pcm0.r.low pcm0.r.high pcm1.l.low
avance logic inc. ALS300 43 appendix d : esp/mpu401 programming guide esp procedure: esp read data procedure: esp_read(return_byte) 1. if i/o read(esp-rd-status) bit 7 = 1 goto 2 else 1 2. return_byte = i/o read(esp-read-data) esp write procedure: esp_write(command/data) 1. if i/o read(esp-wr-status) bit7 = 0 goto 2 else 1 2. i/o write(esp-command/data, co mmand/data) esp reset procedure: esp_reset( ) 1. i/o write(esp-reset-port, 1), and wait 3 us 2. i/o write(esp-reset-port, 0) 3. esp_read(status), if status = aah goto 4 else 3 4. end of reset you can use esp_reset() procedure to immediately terminate the special dma transfer. digitized sound transfer method: 1. direct mode esp is programmed to do audio input/output on each command. all delay time is controlled by cpu delay loop or timer interrupt. only 8 bit mono input/output is supported. output: a. esp_write(10h) b. esp_write(next 8 bit mono pcm) c. wait until next sample time, goto a. 2. dma mode 2.1 normal dma mode esp is programmed to make one transfer with a specified block size. at the end of transfer, the esp will generate an interrupt and wait for next command. 2.2 continuous dma mode esp is programmed to make continuous transfer to/from codec. after each transfer of a specified block size, esp will generate an interrupt and continue the next transfer of the same block size after the interrupt is acknlwoedged. there are two ways to terminate continuous dma mode transfer.
avance logic inc. ALS300 44 1.program esp to switch to normal dma mode transfer. at the end of the current dma transfer, esp will exit from continuous dma mode and continue to transfer using the specified normal dma mode. 2.send the exit continuous command. the esp will exit continuous dma mode at the end of current block and terminate the transfer. 2.3 special dma mode once esp is in the special dma mode, it w ill not a ccept any further co mmands or data until the dma mode is terminated by either 1. non-continuous special dma mode w ill exit special dma mode auto matically at the end of transfer. or 2. for continuous special dma mode, a esp_reset() is needed to exit spec ial dma mode. the esp_reset() will only stop special dma transfer, all other parameters remain the same. i/o transfer rate setup: either 1. sound blaster pro (time constant) time constant = 256d - (1,000,000d / ( channel * sampling rate)) channel = 1 for mono or bx,cx type dma co mmand, 2 for stereo a. esp_write(40h) b. esp_write(time constant) or 2. sound blaster 16 (sampling frequency) output: a. esp_write(41h) b. esp_write(frequency.high) c. esp_write(frequency.low) sampling frequency = 4 khz to 48 khz, either mono or stereo mpu-401 midi programming: 1. mpu-401 pass-thru mode after reset, midi is in pass-thru mode. midiin data is directly connected to midiout data. any write to midi-data will be ignored. midi-c ommand w ill support either midi_reset (0ffh) or enter_uart (03fh). both command will return with interrupt and acknowledge byte (0feh). 2. mpu-401 uart mode after enter uart mode, all write to midi-data will go to midiout fifo, any midiin data will go to midiin fifo. (in special m idi mode, any write to midi-data w ill go to m idiout ram) midi-status bit 7 = midiin fifo empty. midi-status bit 6 = midiout fifo full + midiout fifo not empty when midi_reset midi-status bit 5 = midiout ram full midi interrupt =( midiin fifo not empty & not i/o read(midi-data)) or (midiout ram is not empty in special mpu401 mode) to end the uart mode, send midi_reset (0ffh) to midi-command port. midiin fifo will be flushed, any data in midiout fifo/midiout ram will be output. when both fifo are empty, mpu-401 will enter pass-thru mode .
avance logic inc. ALS300 45 part ii : specification for pci i/f and wave engine dram configuration : 11 x 11 : 4m x 4 (dtype[1,0]=10) casa#/cas0# : a 21 ,a 9 ~ a 0 casb#/cas1# : inactive rasa#/ras# : a 20 ,a 19 ~ a 0 12 x 10 : 4m x 4 (dtype[1,0]=11) casa#/cas0# : a 9 ~ a 0 casb#/cas1# : inactive rasa#/ras# : a 21 ~ a 10 10 x 10 : one 1m x 4 (dtype[1,0]=00) casa#/cas0# : a 9 ~ a 0 (a 20 =0) casb#/cas1# : a 9 ~ a 0 (a 20 =1) rasa#/ras# : a 19 ~ a 10 10 x 10 : two 1m x 4 (dtype[1,0]=01) casa#/cas0# : a 9 ~ a 0 (a 20 =0) casb#/cas1# : a 9 ~ a 0 (a 20 =1) rasa#/ras# : a 19 ~ a 10 dram a ccess mode : mode 1 : dram is controlled by pci dram controller. access : memory read/write. mode 2 : dram is controlled by wave engine. access : program gcr8b to start bus master function. it support write function only. arbitration between pci d/a and sb d/a : pci/sb# ( re-sample source select,gcr8c.28) 0 select sb d/a (default) 1 select pci d/a pci/sb# pci/sb# toggle condition 1 sbvlid low go high edge 0 pcivlid=1 arbitration between opl3 d/a and wave engine d/a : wve/fm# ( re-sample source select,gcr8c.1) 0 select opl3 d/a (default) 1 select wave engine d/a wve/fm# wve/fm# toggle condition 1 fmreq low go high edge 0 (ramw# low go high edge) | (fmpwed#=0) fifo/latch arrangement : ac97 serial output buffer : name size slot no. description indx 8 x 1 1 ac97 cmd/address latch dout 16 x 1 2 ac97 ouput data latch pcilo 16 x 8 3 pci playback left channel fifo pciro 16 x 8 4 pci playback right channel fifo mout 16 x 1 5 modem-out latch indx connect to high byte of 16-bit bus ac97 serial input buffer : name size slot no. description din 16 x 1 2 ac97 input data latch pcili 16 x 8 3 pci record left channel fifo
avance logic inc. ALS300 46 pciri 16 x 8 4 pci record right channel fifo min 16 x 1 5 modem-in latch micin 16 x 8 6 mic-in fifo dram-write fifo for mode 2: (enabled on dram a ccess mode 2) name size description dramo 32 x 2 dram write fifo fifo management : underrun fifo should do the following things : 1.send the current data to ac97 i/f when ac97 i/f read fifo. 2.keep read pointer until new data arrived and set corresponding flag. paused output fifo should do the following things : 1.take the same action as normal condition until fifo is empty. 2.when fifo is empty, keep read pointer until pause command stop. dont set any flag. overrun fifo should do the following things : 1.disable fifo update by ac97 i/f until data is fetched. 2.keep write pointer until data is fetched and set corresponding flag. when transfer stop (gcr85.16/gcr88.16=0), ALS300 will discard arriving data. paused input fifo should do the following things : 1.take the same action as normal condition until fifo is full. 2. when fifo is full, keep write pointer until pause command stop. dont set any flag. ALS300 flush fifo once when starting recording. ALS300 implement sampling rate transformation and data type transformation for playback only. for recording, it is implemented by software. because ALS300 implement dma operation by pci bus master, playback or record by pci command has no compatibility issue and ALS300 support address increment transfer only. all pci playback/record command is continuous except dram-write transfer and non-autoinitialization transfer. non-continuous playback. modem i/o management : there are 3 states for modem i/o : off, standby and transmission. off ignore all modem i/o and ring signal. standtby waiting for ring signal. transmission transmit/r eceive d ata to/from remote modem. state\definition gcr8c.12 gcr8c.11 off 00 standby 01 transmission 10 when a ring-in have detected, rd# will be driven low and ALS300 will generate an irq for service. modem driver will do the following thing to answer the call from remote modem when ring-in irq is served. 1. disable ring-in irq (clear gcr8c.11) 2. enable hook output capab ility and set proper value on h ook. 3. enable modem-in irq. in transmission s tate, ALS300 will generate an irq and set corresponding bit of irq-status if receiving d ata from ac97 serial input. for output , driver handle write operation completely. when transmission is complete, driver will do the following things: 1. disable modem-in irq 2. set hook to inactive s tate. 3. enable ring-in irq. relation of ac-link and internal 16-bit data bus : (implemented in pci) ac link bit 19 ? internal data bus bit 15 ac link bit 18 ? internal data bus bit 14 : : ac link bit 4 ? internal data bus bit 0
avance logic inc. ALS300 47 ac link bit 3 ? (output : stuffed with 0 , input : discarded) : : ac link bit 0 ? (output : stuffed with 0 , input : discarded) pcm sample order: z 8 bit mono byte no. 3210 sample pcm 3 pcm 2 pcm 1 pcm 0 z 8 bit stereo byte no. 3210 sample pcm1.r pcm1.l pcm0.r pcm0.l z 16 bit mono byte no. 3210 sample pcm1.high pcm1.low pcm0.high pcm0.low z 16 bit stereo byte no. 3210 sample pcm0.r.high pcm0.r.low pcm0.l.high pcm0.l.low transformation between different pcm data type : the pcm data type for ac97 is 16-bit signed pcm data. the transformations are described below : unsigned ? signed 16-bit(8-bit) unsigned value signed value ffffh(ffh) 7fffh(7fh) :: 8001h(81h) 0001h(01h) 8000h(80h) 0000h(00h) 7fffh(7fh) ffffh(ffh) :: 0000h(00h) 8000(80h) mono ? stereo duplicated left channel to right channel. 8-bit ? 16-bit stuff low byte with 0. the transformation sequence are : n unsigned ? signed o 8-bit ? 16-bit p mono ? stereo ac97 mixer read procedure : 1.check ac97-status bit 7, if bit7=1 go to 1,else go to 2. 2.write mixer index to ac97-access(bit 24~31) with bit 31=1(read operation) 3.check ac97-status bit 6, if bit 6=0 goto 3, else goto 4. 4.read data from ac97-read. ac97 mixer write procedure : 1.check ac97-status bit 7, if bit 7 =1 go to 1,else go to 2. 2.write index and data to ac97-access with bit 31=0 wave engine ram access : the working ram of wave engine is 128 x 32 ram. it can be a ccessed via address port and 32-bit data port. note for interrupt service routine( isr) and tsr : because ALS300 share one irq line with multiple irq request., the tsr developer will pay more attention to decide which request to be served. for tsr : 1. mask inta# output. (set gcr8c.15) ,check irq-status and acknowledge irqs. 2. call corresponding isr s (higher-priority isr first)
avance logic inc. ALS300 48 3. enable inta# output capability again.(clear gcr.15) and return to main program for isr : 1. serve irq request. power down sequence : n enable power down clock (set rcclken as 1) o wait power down clock stable and power down wave engine/fm/sb/mpu401 p wait 384 clocks of bitclk (at least 31.2us) and power down ac-link q disable 14.318 mhz output (set vco-oscen# as 1) power on sequence : n activate ac-link o enable 14.318mhz output (clear vco-oscen# as 0) p power on sb/wave engine/mpu401/fm (wait for 14.318m clock stable if power on fm) q disable power clock (2mhz) output. (clear rcclken as 0) irq acknowledge method and suggested irq priority for tsr : type priority condition to generate acknowledgment min 0 modem-in data is available write irq-status bit 1 with 1 ring-in 1 ring# input is low write irq-status bit 0 with 1 pci-play 2 end of a block of playback transfer write irq-status bit 3 with 1 micin 3 end of a block of mic-in transfer write irq-status bit 4 with 1 pci-rec 4 end of a block of record transfer write irq-status bit 2 with 1 sb/mpu 5 sb playback/mpu401 write irq-status bit 7 with 1 sb-mixer 6 write sb mixer write irq-status bit 5 with 1 dram 7 end of a block of dram transfer write irq-status bit 6 with 1 0: highest priority 6 : lowest priority memory space and io space in pci : memory space : 2m bytes the starting address is defined in pci configuration registers. this memory space is mapping to dram. ALS300 io space 0 : 64 bytes address byte 3 byte 2 byte 1 byte 0 iobase0+00h ac97-access ( r/w ) iobase0+04h irq- status( r/w ) ac97-status( r ) ac97-read ( r ) iobase0+08h gcr/ram-data ( r/w ) iobase0+0ch reserved gcr/ram-index ( r/w) iobase0 = base address defined in configuration space ? ALS300 support dw/word/byte access. when access pnp alias port for pnp configuration, ALS300 support byte command only. only byte command transformation is permitted for iobase0 + 10h ~23h. sbbase+0~3 is equivalent to oplbase+0~3. ac97-access default : xxxxxxxxh iobase + 00-03h bit type function 31 r/w r/w control , 0 : write 1 : read 30:24 r/w ac97 mixer index 23:16 reserved 15:0 r/w ac97 write data n the programmer should write index and data at the same time or write data before writing index. this ensure index and data will output in the same frame. ac97-read default : xxxxh iobase + 04-05h bit type function 15:0 r data return from ac97 codec ac97-status default : 00h iobase + 06h
avance logic inc. ALS300 49 bit type function 7r indx status 0 : ready for ac97 mixer a ccess 1 : ac97 is busy 6r din status 0 : empty 1 : ac97 mixer data is available 5r mout status 0 : ac97 is ready for modem-out transfer 1 : ac97 modem-out is busy 4 r mpu401 irq flag 0 : no irq 1 : irq generated (for d version only) 3r pcilo/pciro fifo status 0 : empty 1 : non-empty 2r pcili/pciri fifo status 0 : empty 1 : non-empty 1r micin fifo status 0 : empty 1 : non-empty 0r dram fifo status 0 : empty 1 : non-empty n an io-write to ac97-access with bit 31=1 will clear bit 6. o read iobase+4~7 will clear bit 4 automatically. (for d version) irq-status default : 00h iobase + 07h bit type function 7 r/w sb/mpu irq flag : 0 : normal 1 : irq generated 6 r/w dram irq flag : 0 : normal 1 : irq generated 5 r/w sb-mixer irq flag : 0 : normal 1 : irq generated 4r/w micin irq flag : 0 : normal 1 : irq generated 3r/w pci-play irq flag : 0 : normal 1 : irq generated 2r/w pci-rec irq flag : 0 : normal 1: irq generated 1r/w modem-in irq flag : 0 : normal 1 : irq generated 0r/w ring-in irq flag : 0 : normal 1 : irq generated n write this register with 1 will clear the corresponding irq flag. write this register with 0 will keep the corresponding irq flag. o when bit 7 is set, tsr should read mx82 to identify the requesting device. write 1 to this bit will clear the flag too. tsr should acknowledge the irq by access acknowledge port in sb logic. note that irq request from sb core is routed to inta# directly. bit 7 is a flag only ? the mpu401 irq status located at different register for different version. version location acknowledge a irq-status bit 7 write irq-ststus with bit 7 as 1 c irq-status bit 7 write irq-ststus with bit 7 as 1 d ac97-status bit 4 read ac97-ststus once e,f,g iobase+e bit 4 read iobase+c~e gcr/ram-data default : xxxxxxxxh iobase + 08-0bh bit type function 31:0 r/w gcr/wave engine ram data gcr/ram-index default : xxh iobase + 0ch bit type function 7 r/w gcr/wave engine select 0 : wave engine ram 1 : gcr 6:0 r/w gcr/wave engine ram index ext-irq-status default : 00h iobase + 0eh bit type function 7:5 reserved 4r mpu401 irq flag : 0 : normal 1 : irq generated (implemented for version latter than e) 3:1 reserved 0r fflp (internal flip-flop , implemented for version latter than f ) ? read iobase+0eh will clear bit 4 automatically bit 0 will use as low/high byte pointer when driver take io trapping skill. ALS300 global control register array : index port : gcr/ram-index
avance logic inc. ALS300 50 data port : gcr/ram-data gcr80 default xxxxxxxxh playback starting address bit type function 31:2 r/w playback starting address sa[31..2] 1:0 reserved gcr81 default xxxxxxxxh playback end address bit type function 31:2 r/w playback end address ea[31..2] 1:0 reserved gcr82 default : 0000xxxxh playback control bit type function 31:22 r/w pci playback sampling rate pcifs[9..0] 21 r/w pcilo/pciro fifo threshold control 0 : 4dw 1 : 2dw 20 r/w pcm type 1 : unsigned 0 : signed 19 r/w mono/stereo select : 1 : mono 0 : stereo 18 r/w 8/16 bit select : 1 : 8-bit 0 : 16-bit 17 r/w playback fifo control 0 : normal 1 : pause 16 r/w playback transfer control 0 : stop 1 : start 15:2 r/w playback block length bl[15..2] 1:0 r reserved, read as 1 n pcifs formula : bit 9 1 d=2 0d=1 bit 8 1 o=1 0o=0 bit7~0 n pcifs = f clk /(m*18*d) where m = (n+1)*2+o , f clk = 14.318 mhz o when (no. of byte in playback fifo) threshold,ALS300 will generate a request to bus master for data transfer until playback fifo is full. the bus master will transfer data from system memory to ALS300 if bit 16=1. p block length = (# of data byte ) - 1 (ex. 0 fffh ? 4k bytes) ALS300 will generate an interrupt for every specified block size transfered. gcr83 default xxxxxxxxh record starting address bit type function 31:2 r/w record starting address sa[31..2] 1:0 reserved gcr84 default xxxxxxxxh record end address bit type function 31:2 r/w record end address ea[31..2] 1:0 reserved gcr85 default : 0000xxxxh record control bit type function 31:22 reserved 21 r/w record fifo threshold control 0 : 4 dw 1 : 2 dw 20:18 reserved 17 r/w record fifo control 0 : normal 1 : pause 16 r/w record transfer control 0 : stop 1 : start 15:2 r/w record block length bl[15..2] 1:0 r reserved, read as 1 n when (no. of byte in record fifo) 3 threshold,ALS300 will generate a request to bus master for data transfer until record fifo is empty. the bus master will transfer data from ALS300 to system memory if enabled by bit 16. o block length = (# of data byte ) - 1 (ex. 0 fffh ? 4k bytes) ALS300 will generate an interrupt for every specified block size transfered.
avance logic inc. ALS300 51 gcr86 default xxxxxxxxh mic record starting address bit type function 31:2 r/w mic-in starting address sa[31..2] 1:0 reserved gcr87 default xxxxxxxxh mic record end address bit type function 31:2 r/w mic-in end address ea[31..2] 1:0 reserved gcr88 default : 0000xxxxh mic record control bit type function 31:22 reserved 21 r/w micin fifo threshold control 0 : 4 dw 1 : 2 dw 20:18 reserved 17 r/w micin fifo control 0 : normal 1 : pause 16 r/w mic-in transfer control 0 : stop 1 : start 15:2 r/w mic-in block length bl[15..2] 1:0 r reserved, read as 1 n when (no. of byte in mic-in fifo) 3 threshold,ALS300 will generate a request to bus master for data transfer until mic-in fifo is empty. the bus master will transfer data from ALS300 to system memory if enabled by bit 16. o block length = (# of data byte ) - 1 (ex. 0 fffh ? 4k bytes) ALS300 will generate an interrupt for every specified block size transfered. gcr89 default xxxxxxxxh dram-write starting address bit type function 31:2 r/w dram-write starting address sa[31..2] 1:0 reserved gcr8a default xxxxxxxxh dram-write end address bit type function 31:2 r/w dram-write end address ea[31..2] 1:0 reserved n after whole buffer is accessed, gcr8b.16 is cleared. gcr8b default : 0010xxxxh dram-write control bit type function 31:24 reserved 23:22 r/w dram type select (dtype[1..0]) 0 0 one 1m x 4 (10 x 10) 0 1 two 1m x 4 (10 x 10) 1 0 4m x 4 (11 x 11) 1 1 4m x 4 (12 x 10) 21:20 r/w muxra delay select 0 0 6 ns 0 1 10 ns (default) 1 0 14 ns 1 1 18 ns 19:18 reserved 17 r/w dram access mode 0 : mode 1 1 : mode 2 16 r/w dram-write transfer control 0 : stop 1 : start (effective when bit 17 =1) 15:2 r/w dram-write block length bl[15..2] 1:0 r reserved, read as 1 n when dram-write fifo is not full ,ALS300 will generate a request to bus master for data transfer until dram-write fifo is full. the bus master will transfer data from ALS300 to system memory if enabled by bit 16. o block length = (# of data byte ) - 1 (ex. 0 fffh ? 4k bytes) ALS300 will generate an interrupt for every specified block size transfered. p sw should detect dram type when system is power-on.
avance logic inc. ALS300 52 q it spend 12 clocks of bitclk (12.288mhz) to switch between dram a ccess mode 1 and mode 2. the programmer should wait until the state transition is complete. gcr8c default xxxx0011h mis cellaneous control bit type function 31:30 reserved 29 r 279/a79 snoop control 0 : enable 1 : disable 28 r pci/sb# status 1 : pci wave 0 : sb wave 27 reserved 26 r ALS300 clock source 0 : internal pll 1 : external crystal 25 r pnp port ioen gating control 0 : no gating 1 : gating 24 r pnp emulation h/w control bit 0 : enable 1 : disable 23 r/w pll or crystal oscillator control (vco-oscen#) 0:enable(default) 1:disable 22 r/w rc oscillator control (rcclken) 0:disable(default) 1:enable 21 r/w music mute control (mmute#) 1 : normal 0 : mute (default : 1) 20 r/w voice mute control (vmute#) 1 : normal 0 : mute (default : 1) 19:16 r chip revision number 15 r/w inta# mask control 0 enable irq output 1 disable irq output (drive inta# to inactive state) version f or latter : 1 enable irq output 0 disable irq output (drive inta# to inactive state) 14 r/w ac97 interface loop-back control ( aclb ) 0 : normal 1 : loop-back (ac serial output ? ac serial input) 13 r/w fifo loop-back control 0 : disable 1 : enable (pcilo ? pcili,pciro ? pciri,pcilo ? micin) 12 r/w min irq control 0 : disable 1 : enable 11 r/w ring-in irq control 0 : disable 1 : enable 10 r/w digital sum control 0pcm sum = pcm voice + pcm music 1pcm sum = pcm voice /2 + pcm music /2 9 r/w legacy-dma read control 0 : disable (default) 1 : enable 8 r/w special data latch control 0 : normal 1 : sis5513 7 r level latch from hook when system reset. 6:5 r/w ac97 reset mode select 00 : normal 01 : warm reset 10 : cold reset 11 : reserved 4 r/w pcm playback mute control 0 : mute 1 : unmute 3 r/w hook output capab ility control 0 : float 1 : drive bit 2 to pad 2 r/w data drived to hook 1 r synthesizer mux status (wve/fm#) 1 : internal wave engine 0 : fm synthesizer 0 r/w wave engine mute control (wmute#) 0 : mute 1 : normal n chip-id will increase by 1 when chip tape-out. o wvereq low-go-high edge will select wave engine as musical synthesizer. p actually the pnp emulation control signal , pnpen, is pnpen = bond & (!gcr8c.24&gcr8c.29) q when gcr8c.5 or gcr8c.6 is set, it will be cleared when ac97 reset operation is complete. r gcr8c.24 is latched from dq0 when system reset. gcr8c.25 is latched from dq1 when system reset. gcr8c.26 is latched from dq2 when system reset. gcr8d default : 00xxxxxxh dram address of mode 2 a ccess bit type function 31:21 reserved 20:2 r/w dram address da[20..2] (byte address) 1:0 r read as 0
avance logic inc. ALS300 53 when ALS300 start dram data transfer, da[20..2] is the starting address of the dram memory space. this address will increase automatically during the transfer period. sw should update this register content before the beginning of next block transfer. gcr8e default : xxxxxxxxh mus ic/voice volume bit type function 31:27 r/w music-left volume in 1.5db step , 00h : 0db , 1fh : -46db 26:24 reserved 23:19 r/w music-right volume in 1.5db step , 00h : 0db , 1fh : -46db 18:16 reserved 15:11 r/w voice-left volume in 1.5db step , 00h : 0db , 1fh : -46db 10:8 reserved 7:3 r/w voice-right volume in 1.5db step , 00h : 0db , 1fh : -46db 2:0 reserved n sw should set a default volume after system reset. gcr8f default : xxxxxxxxh modem i/o bit type function 31:16 w modem-out data bit 15~0 15:0 r modem-in data bit 15~0 gcr90 default : xx5a0000h test mode register bit type function 31:24 r/w reserved 23:22 r/w rc oscillator output divider 00:2 01:4 10:8 11:16 21:20 r/w vco v-i stage resistor select 00:5.2k 01:4.5k 10:3.7k 11:3k 19 r/w rc oscillator input current control 0:30u 1:45u 18 r/w vco input current control 0:30u 1:45u 17:16 r/w band gap resister control 00:2.5k 01:2.2k 10:1.9k 11:1.6k 15:8 r/w sb test mode register (normal = 00h) 7:6 r/w wave engine test mode register 5 r/w pll test (plltest) 0 : 14.318m/256 1: 2m/32 4:0 r/w wave engine test mode register (normal = 00h) n plltest 0 xclk output 14.318m/256 clock 1 xclk output osc2 clock (2m/32 hz) gcr91 default : 00ffffffh dma 0 starting address bit type function 31:24 reserved 23:0 r dma channel 0 starting address sa0[23..0] n stuff sa0[31..24] with 0 when implemented. gcr92 default : 0000 ffffh dma 0 mode register and base byte count bit type function 31:22 reserved 21 r address increment/decrement select. 0 : increment 1 : decrement 20 r auto-initialization enable 0 : disable 1 : enable 19:18 r transfer mode 01 : write 10 : read others : reserved 17:16 reserved 15:0 r dma channel 0 base byte count bbc0[15..0] n write transfer ALS300 ? memory read transfer ALS300 ? memory gcr93 default : 00ffffffh dma 1 starting address bit type function 31:24 reserved 23:0 r dma channel 1 starting address sa1[23..0] n stuff sa1[31..24] with 0 when implemented. gcr94 default : 0000 ffffh dma 1 mode register and base byte count bit type function
avance logic inc. ALS300 54 31:22 reserved 21 r address increment/decrement select. 0 : increment 1 : decrement 20 r auto-initialization enable 0 : disable 1 : enable 19:18 r transfer mode 01 : write 10 : read 17:16 reserved 15:0 r dma channel 1 base byte count bbc1[15..0] n write transfer ALS300 ? memory read transfer ALS300 ? memory gcr95 default : 00ffffffh dma 3 starting address bit type function 31:24 reserved 23:0 r dma channel 3 starting address sa3[23..0] n stuff sa[31..24] with 0 when implemented. gcr96 default : 0000 ffffh dma 3 mode register and base byte count bit type function 31:22 reserved 21 r address increment/decrement select. 0 : increment 1 : decrement 20 r auto-initialization enable 0 : disable 1 : enable 19:18 r transfer mode 01 : write 10 : read 17:16 reserved 15:0 r dma channel 3 base byte count bbc3[15..0] n write transfer ALS300 ? memory read transfer ALS300 ? memory gcr97 default xx004071h bit type function 31:24 r pnp read port address ra[9..2], ra[1..0]=[1,1] 23:20 reserved 19 r/w sbbase decode control 0 : enable 1 : disable 18 r/w oplbase decode control 0 : enable 1 : disable 17 r/w gamebase decode control 0 : enable 1 : disable 16 r/w mpubase decode control 0 : enable 1 : disable 15:8 r/w gamebase[10..3] (default : 40h) 7:0 r/w oplbase[10..3] (default : 71h) n when pnp emulation is disabled, sw can a ccess pnp alias ports (gcr99.31~16) to configure sb logic. the configuration process is identical to that of pnp specification except the io address. the new address map are : gcr99.31~24 write data port (a79h) note that there is no alias port for pnp read data port. in alias configuration process, ALS300 will not catch the data that writing to pnp registers. ? bit 19~16 control the legacy io gcr98 default b0002233h bit type function 31 r dma 3 mask 1 : mask dma oper ation (default : 1) 30 reserved 29 r dma 1 mask 1 : mask dma oper ation (default : 1) 28 r dma 0 mask 1 : mask dma oper ation (default : 1) 27 reserved 26:24 r/w sb dma (pnp0-74.2~0) (default 00) 23 r/w sb io range check control(pnp0-31.1) 0 : disable 1 : enable 22 r/w opl3 io range check control(pnp1-31.1) 0 : disable 1 : enable 21 r/w game-port io range check control(pnp2-31.1) 0 : disable 1 : enable 20 r/w mpu401 io range check control(pnp3-31.1) 0 : disable 1 : enable 19 r/w sb activate (pnp0-30.0) 0 : disable 1 : enable 18 r/w opl3 activate (pnp1-30.0) 0 : disable 1 : enable
avance logic inc. ALS300 55 17 r/w game-port activate (pnp2-30.0) 0 : disable 1 : enable 16 r/w mpu401 activate (pnp2-30.0) 0 : disable 1 : enable 15 reserved 14 r dma channel group enable 0 : enable 1 : disable 13:8 r/w sbbase[9..4] (default : 22h) 7:6 r pnp device number (pnp07[1..0]) 5:0 r/w mpubase[9..4] (default : 33h) n when dma group enable bit (gcr98.14) is set, it w ill disable dma 0,1,3 emu lation. when this bit is clear, dma emu lation is controlled by mask bit (gcr98.31,29,28). o sb dma 000 dma 0 001 dma 1 011 dma 3 100 no dma select others reserved p if auto-initialized mode is disabled, gcr98.31,29,28 will be set when tc=1. gcr99 default 00000000h bit type function 31:24 w a79h alias port 23:16 w 279h alias port 15:6 r/w ddma base address ddmaba[15..6] 5:1 reserved 0r/w ddma enable 0 : disable 1 : enable (default : 0) n when ddma is enabled, ALS300 ignore legacy dmac io cycle and c laim ddma io cycle. o when access 279h/a79h alias port, it is strongly commended to issue byte command. gcr9a default xxxxxxxxh pci-play block counter bit type function 31:16 reserved 15:0 r value of block counter gcr9b default xxxxxxxxh pci-rec block counter bit type function 31:16 reserved 15:0 r value of block counter gcr9c default xxxxxxxxh mic-in block counter bit type function 31:16 reserved 15:0 r value of block counter gcr9d default xxxxxxxxh dram block counter bit type function 31:16 reserved 15:0 r value of block counter gcr9e default xxxxxxxxh wave engine test register 0 bit type function 31:0 r/w for test mode only gcr9f default xxxxxxxxh wave engine test register 1 bit type function 31:8 reserved 7:0 r/w for test mode only dma emulation design suggestion : n cbc decrease by 1 each time when 1-byte transfer is complete. o ca will decrease/increase by 1 each time when drqx is activated. ALS300 will discard ca [1..0] for fetching next data. one layer latch is enough for dma emu lation. pci configuration registers : vendor id register :
avance logic inc. ALS300 56 index : 00-01h read only bit 15~8 40h (vendor id high byte) bit 7~0 05h (vendor id low byte) device id register : index : 02-03h read only bit 15~8 03h (device id high byte) bit 7~0 00h (device id low byte) command register : default 00h index : 04-05h r/w bit 2~0 0 disable 1enable bit 15~3 reserved, read as 0 bit 2 bus master enable bit 1 memory access enable bit 0 io access enable write pci configuration register indexed 04h will reset ALS300 bus master. status register : index : 06-07h read only default 00h read : bit 15~11 reserved ,read as 0 bit 10,9 devsel# timing read as 01 (medium timing) bit 8 data parity reported 0 normal 1 data parity error detected bit 7~0 reserved, read as 0 write one bit with 1 will clear this bit. class code register : index : 09~0bh read only read as 040100h (multimedia audio device) latency timer register : index: 0dh r/w default : 00h bit 7~4 no. of pci clock that ALS300 retain ownership of bus. bit 3~0 reserved , read as 0 base address register 0 : (io space 0) index : 10~13h r/w default : 0001h bit 0 read as 1 (io base address indicator) bit 4~1 reserved, read as 0 bit 31~5 iobase bit 31~5 (32-bytes io space) base address register 1 : (memory space) index 14~17h r/w default : 0000h bit 20~0 read as 0 bit 31~21 drambase bit 31~21 (2m bytes) subsystem vendor id : index : 2c~2dh read only default : 4005h bit 15~0subsystem vendor id if external e 2 prom is enabled, subsystem vendor id will be load from e 2 prom after reset. subsystem id : index : 2e~2fh read only default : 0000h bit 15~0subsystem id
avance logic inc. ALS300 57 if external e 2 prom is enabled, subsystem id will be load from e 2 prom after reset. interrupt line register : index : 3ch r/w default : 0x00 bit 7~0 irq number interrupt pin register : index : 3dh read only default : 01h (inta#) pnp register array : (write only pnps[1..0]=[1x]) index register 279h (write only) write data port a79h (write only) pnp00 read port register write only (enabled when pnps[1..0]=1x) bit 7~0 gcr97.31~24 pnp07 device number register write only(enabled when pnps[1..0]=1x) bit 7~2 reserved bit 1~0 gcr98.7~6 pnp0-30 sb activate register write only(enabled when pnps[1..0]=1x) bit 0 gcr98.19 bit 7~1 reserved pnp0-31 sb io range check write only(enabled when pnps[1..0]=1x) bit 7~2 reserved bit 1 gcr98.23 bit 0 reserved pnp0-60 sb base-high write only(enabled when pnps[1..0]=1x) bit7~2 reserved bit 1 sbbase.9 (gcr98.13) bit 0 sbbase.8 (gcr98.12) pnp0-61 sb base-low write only (enabled when pnps[1..0]=1x) bit 7~4 sbbase.7~4 (gcr98.11~8) bit 3~0 reserved pnp0-74 sb dma write only (enabled when pnps[1..0]=1x) bit7~3 reserved bit 2~0 sbdma (gcr98.26~24) pnp1-30 opl3 activate register write only (enabled when pnps[1..0]=1x) bit 7~1 reserved bit 0 gcr98.18 pnp1-31 opl3 io range check write only(enabled when pnps[1..0]=1x) bit 7~2 reserved bit 1 gcr98.22 bit 0 reserved pnp1-60 opl3 base-high write only(enabled when pnps[1..0]=1x) bit7~3 reserved bit 2~0 oplbase.10~8 (gcr97.7~5) pnp1-61 opl3 base-low write only (enabled when pnps[1..0]=1x) bit 7~3 oplbase.7~3 (gcr97.4~0)
avance logic inc. ALS300 58 bit 2~0 reserved pnp2-30 game-port activate register write only (enabled when pnps[1..0]=1x) bit 7~1 reserved bit 0 gcr98.17 pnp2-31 game-port io range check write only(enabled when pnps[1..0]=1x) bit 7~2 reserved bit 1 gcr98.21 bit 0 reserved pnp2-60 game-port base-high write only(enabled when pnps[1..0]=1x) bit7~3 reserved bit 2 gamebase.10~8 (gcr97.15~13) pnp2-61 game-port base-low write only (enabled when pnps[1..0]=1x) bit 7~3 gamelbase.7~3 (gcr97.12~8) bit 2~0 reserved pnp3-30 mpu401 activate register write only (enabled when pnps[1..0]=1x) bit 7~1 reserved bit 0 gcr98.16 pnp3-31 mpu401 io range check write only(enabled when pnps[1..0]=1x) bit 7~2 reserved bit 1 gcr98.20 bit 0 reserved pnp3-60 mpu401 base-high write only (enabled when pnps[1..0]=1x) bit7~2 reserved bit 1~0 mpubase.9~8 (gcr98.5~4) pnp3-61 mpu401 base-low write only (enabled when pnps[1..0]=1x) bit 7~4 mpubase.7~4 (gcr98.3~0) bit3~0 reserved
avance logic inc. ALS300 59 appendix a : pnp and dma emulation pnp state : pnp state pnps[1..0] wait-for-key 00 sleep 01 configuration 10 isolation 11 the pnp specification define pnp register indexed 00h~2fh as card level register, others as device level register. for simplicity, we define pnpxx : pnp card level register xx, where xx is in range of 00h to 2fh. pnpy-xx : pnp device y register xx, where xx is in range of 30h to ffh note that pnpxx and pnpy-xx implemented in pci interface are write-only for pnp compatibility. the write operation is enabled only when pnps[1..0]=1x. ALS300 pnp emulation block decode the following address range for sb logic when gcr9a.1=0 : address length type enabled condition sbbase[15..0] 16 bytes io r/w (pnp0-30.0=1)|(pnp0.31.1=1) oplbase[15..0] 4 bytes io r/w (pnp1-30.0=1)|(pnp1-31.1=1) gamebase[15..0] 8 bytes io r/w (pnp2-30.0=1)|(pnp2-31.1=1) mpubase[15..0] 4 bytes io r/w (pnp3-30.0=1)|(pnp3-31.1=1) 279h 1 byte io w *note* a79h 1 byte io w *note* ra[9..0] 1 byte io r pnps[1..0]=[1x] note : n ALS300 claim write cycle of a79h only when [(pnps[1..0]=01) & csn0&(pnp index = 03)] where csn0 is the flag indicating csn=0. csn0=1 means csn = 0. for other conditions, ALS300 snoop it only. remember that ALS300 always forward write cycle of a79h to sb logic. o for 279h decoding, ALS300 always snoop and forward to sb core logic. p for pnp read port decoding, ALS300 snoop and forward to sb logic only when pnps[1..0]=1x. dma emulation by bus master function : ALS300 implement 2 types of dma emu lation scheme : legacy dma and distributed dma (ddma). ALS300 emu late the assigned channel (0,1,3) only. internal registers/flags : retry the flag decide whether read status from 8237 or not.(effective in legacy- dma) 1 enabled read (default) 0 disable read fflp 1_bit flip-flop function as low/high byte pointer for dma io register (00~07h) (effective in legacy-dma) write 0x0c will clear fflp to 0.fflp is default 0 after reset. any a ccess to 00h~07h will toggle its value. ca 24-bit address counter of dma emu lation. cbc 16-bit byte counter of dma emu lation. dma emulation scheme for legacy-dma mode and ddma mode : z legacy-dma mode : ALS300 decode the following io command : address command function enabled 00h io write fflp=0: write to gcr91.7~0 fflp=1: write to gcr91.15~8 always 00h io read fflp=0: read from ca.7~0 fflp=1: read from ca.15~8 sbdma = 000 01h io write fflp=0: write to gcr92.7~0 fflp=1: write to gcr92.15~8 always 01h io read fflp=0: read from cbc.7~0 sbdma
avance logic inc. ALS300 60 fflp=1: read from cbc.15~8 = 000 87h io write write to gcr91.23~16 always 02h io write fflp=0: write to gcr93.7~0 fflp=1: write to gcr93.15~8 always 02h io read fflp=0: read from ca.7~0 fflp=1: read from ca.15~8 sbdma = 001 03h io write fflp=0: write to gcr94.7~0 fflp=1: write to gcr94.15~8 always 03h io read fflp=0: read from cbc.7~0 fflp=1: read from cbc.15~8 sbdma = 001 83h io write write to gcr93.23~16 always 06h io write fflp=0: write to gcr95.7~0 fflp=1: write to gcr95.15~8 always 06h io read fflp=0: read from ca.7~0 fflp=1: read from ca.15~8 sbdma = 003 07h io write fflp=0: write to gcr96.7~0 fflp=1: write to gcr96.15~8 always 07h io read fflp=0: read from cbc.7~0 fflp=1: read from cbc.15~8 sbdma = 003 82h io write write to gcr95.23~16 always 08h io read return the combined status $$$ 08h io write write bit 2 to gcr98.14 always 0ah io write bit 1, bit 0 0 0 write bit 2 to gcr98.28 0 1 write bit 2 to gcr98.29 1 0 no action 1 1 write bit 2 to gcr98.31 always 0bh io write bit 1, bit 0 0 0 write bit 5~2 to gcr92 bit 21~18 0 1 write bit 5~2 to gcr94 bit 21~18 1 0 no action 1 1 write bit 5~2 to gcr96 bit 21~18 always 0ch io write clear fflp to 0 always 0dh io write clear fflp,dma group enable(gcr98.14),dma status and set mask bit (gcr98.31,29,28) always 0eh io write clear mask bit (gcr98.31,29,28) always 0fh io write write all mask bit (write bit 3,1,0 to gcr98.31,29,28) always for dma register access, ALS300 take different action for read and write operation : write operation snoop it,fetch data and save to corresponding registers. read operation controlled by gcr8c.9 when legacy-dma read is enabled, ALS300 w ill claim the read command for dma s tatus read operation, ALS300 will take action depending on retry. if retry=1, ALS300 issue pci retry to terminate the cycle and request the bus. when granting the bus, ALS300 issue 8237 status read cycle to get the status. after getting the status, ALS300 combined it with current status of the emulated dma channel and clear retry. the constructed d ata is : sbdma=000 replace 8237-s tatus bit 4,0 with internal status sbdma=001 replace 8237-s tatus bit 5,1 with internal status sbdma=011 replace 8237-s tatus bit 7,3 with internal status if retry=0, ALS300 return the status. after status is read, retry is set again. for current address/byte read, ALS300 claim the command for the dma channel emulated only. for io read from 87h.82h/83h, its not n ecessary to claim these io command. z ddma mode :
avance logic inc. ALS300 61 ALS300 implemented ddma register for system chipset a ccess. the ddma address is calculated as follow : ddmabase[31..16]=0 ddmabase[15..6]=gcr99.15~6 ddmabase[5..4]= 00 sbdma=000 01 sbdma=001 11 sbdma=011 ddmabase[3..0] map to the following oper ation. ddmabase[3..0] type function 00h w sbdma=000 write to gcr91.7~0 sbdma=001 write to gcr93.7~0 sbdma=011 write to gcr95.7~0 00h r read from ca.7~0 01h w sbdma=000 write to gcr91.15~8 sbdma=001 write to gcr93.15~8 sbdma=011 write to gcr95.15~8 01h r read from ca.15~8 02h r/w sbdma=000 a ccess gcr91.23~16 sbdma=001 a ccess gcr93.23~16 sbdma=011 a ccess gcr95.23~16 03h reserved 04h w sbdma=000 write to gcr92.7~0 sbdma=001 write to gcr94.7~0 sbdma=011 write to gcr96.7~0 04h r read from cbc.7~0 05h w sbdma=000 write to gcr92.15~8 sbdma=001 write to gcr94.15~8 sbdma=011 write to gcr96.15~8 05h r read from cbc.15~8 06h~07h reserved 08h w write bit 2 to gcr98.14 08h r read internal dma s tatus 09h w terminate the cycle only 0ah reserved 0bh w sbdma=000 write bit5~2 to gcr92.21~18 sbdma=001 write bit5~2 to gcr94.21~18 sbdma=011 write bit5~2 to gcr96.21~18 0ch reserved 0dh w clear fflp,dma group enable(gcr98.14),dma status and set mask bit (gcr98.31,29,28) 0e reserved 0f w sbdma=000 write bit 0 to gcr98.28 sbdma=001 write bit 0 to gcr98.29 sbdma=011 write bit 0 to gcr98.31 for dma comp atibility issue, ca/cbc load starting value according the condition as follow : source enabled condition gcr91 gcr92 (sbdma=0)&[(write pnp0-74) | (io write gcr91,gcr92.15~0) | (tc=1 in auto-initialization mode)] gcr93 gcr94 (sbdma=1)&[(write pnp0-74) | (io write gcr93,gcr94.15~0) | (tc=1 in auto-initialization mode)] gcr95 gcr96 (sbdma=3)&[(write pnp0-74) | (io write gcr95,gcr96.15~0) | (tc=1 in auto-initialization mode)] note : tc=1 when cbc reach ffffh.
avance logic inc. ALS300 62 appendix b : ALS300 frequency code table code fs(khz) code fs(khz) code fs(khz) code fs(khz) 162 3.997 14b 5.199 134 7.434 11d 13.040 062 4.017 04b 5.233 034 7.504 01d 13.257 161 4.038 14a 5.268 133 7.576 11c 13.482 061 4.058 04a 5.303 033 7.648 01c 13.714 160 4.079 149 5.339 132 7.723 11b 13.955 060 4.100 049 5.375 032 7.798 01b 14.204 15f 4.121 148 5.411 131 7.876 11a 14.463 05f 4.143 048 5.448 031 7.954 01a 14.730 15e 4.165 147 5.486 130 8.035 119 15.008 05e 4.187 047 5.524 030 8.117 019 15.297 15d 4.209 146 5.563 12f 8.200 118 15.597 05d 4.231 046 5.602 02f 8.286 018 15.909 15c 4.254 145 5.641 12e 8.373 117 16.233 05c 4.277 045 5.682 02e 8.462 017 16.572 15b 4.300 144 5.723 12d 8.553 116 16.924 05b 4.323 044 5.764 02d 8.646 016 17.292 15a 4.347 143 5.806 12c 8.741 115 17.676 05a 4.371 043 5.849 02c 8.838 015 18.078 159 4.395 142 5.892 12b 8.938 114 18.499 059 4.419 042 5.936 02b 9.039 014 18.939 158 4.444 141 5.981 12a 9.143 113 19.401 058 4.469 041 6.026 02a 9.249 013 19.886 157 4.494 140 6.072 129 9.358 112 20.396 057 4.520 040 6.119 029 9.470 012 20.993 156 4.545 13f 6.166 128 9.584 111 21.498 056 4.571 03f 6.214 028 9.700 011 22.096 155 4.598 13e 6.263 127 9.820 110 22.727 055 4.625 03e 6.313 027 9.943 010 23.395 154 4.652 13d 6.364 126 10.069 10f 24.104 054 4.679 03d 6.415 026 10.198 00f 24.858 153 4.707 13c 6.467 125 10.330 10e 25.659 053 4.735 03c 6.520 025 10.466 00e 26.515 152 4.763 13b 6.574 124 10.605 10d 27.429 052 4.792 03b 6.629 024 10.749 00d 28.409 151 4.821 13a 6.684 123 10.896 10c 29.461 051 4.850 03a 6.741 023 11.048 00c 30.594 150 4.880 139 6.799 122 11.203 10b 31.818 050 4.910 039 6.857 022 11.363 00b 33.143 14f 4.941 138 6.917 121 11.528 10a 34.584 04f 4.972 038 6.978 021 11.698 00a 36.156 14e 5.003 137 7.039 120 11.872 109 37.878 04e 5.034 037 7.102 020 12.052 009 39.772 14d 5.066 136 7.166 11f 12.238 108 41.805 04d 5.099 036 7.231 01f 12.429 008 44.191 14c 5.132 135 7.298 11e 12.626 107 46.791 04c 5.165 035 7.365 01e 12.830
avance logic inc. ALS300 63 code fs(khz) code fs(khz) code fs(khz) code fs(khz) 231 3.977 225 5.233 219 7.649 20d 14.205 330 4.018 324 5.303 318 7.799 30c 14.731 230 4.059 224 5.375 218 7.955 20c 15.297 32f 4.100 323 5.448 317 8.117 30b 15.909 22f 4.146 223 5.524 217 8.286 20b 16.572 32e 4.187 322 5.602 316 8.462 30a 17.292 22e 4.231 222 5.682 216 8.646 20a 18.078 32d 4.277 321 5.764 315 8.838 309 18.939 22d 4.323 221 5.849 215 9.039 209 19.886 32c 4.371 320 5.936 314 9.250 308 20.903 22c 4.419 220 6.026 214 9.470 208 22.096 32b 4.469 31f 6.119 313 9.701 307 23.396 22b 4.520 21f 6.215 213 9.943 207 24.858 32a 4.572 31e 6.313 312 10.198 306 26.515 22a 4.625 21e 6.415 212 10.497 206 28.409 329 4.679 31d 6.520 311 10.749 305 30.594 229 4.735 21d 6.629 211 11.048 205 33.144 328 4.792 31c 6.741 310 11.364 304 36.157 228 4.850 21c 6.857 210 11.698 204 39.772 327 4.910 31b 6.978 30f 12.052 303 44.191 227 4.972 21b 7.102 20f 12.429 203 32.000 326 5.035 31a 7.232 30e 12.830 202 16.000 226 5.099 21a 7.365 20e 13.258 201 8.000 325 5.165 319 7.504 30d 13.715 000 48.000
avance logic inc. ALS300 64 appendix c : register contents of ALS300 wave engine wave engine ram index : (bit 7 = 0) iobase+8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 channel number (n) register index n : channel number of wave engine note : sw should set all ram to their default value to avoid causing noise. register 0 default value : 00000000h bit type function 31 reserved 30:16 r/w repeat offset (ro) 15 reserved 14:0 r/w 2s complement of samples per instrument (tl) n ro is the starting point (in sample) in the wave-form of instrument that could repeat. register 1 default value : 00000000h bit type function 31 r/w key on control (kon) 1 : key on 0 : key off 30:28 r/w frequency modulation coefficient (fmc) 27 r/w 8-bit flag (f8) 1 : 8-bit data 0 : 10-bit or 12-bit data 26:24 r/w amplitude modulation coefficient (amc) 23:21 r/w modulation tone (mt) 20:0 r/w starting address of wave samples (sa) n fmc/amc table fmc/amc am magnitude fm percent (fn<180h) fm percent (fn 3 180h) 0 0 db 0 % 0 % 1 1.78 db 0.8 % 1.6 % 2 2.91 db 1.2 % 2.0 % 3 3.66 db 2.0 % 3.1 % 4 4.50 db 2.7 % 3.9 % 5 5.91 db 5.9 % 8.6 % 6 7.41 db 11.7 % 17.2 % 7 11.92 db 23.4 % 34.4 %
avance logic inc. ALS300 65 am fm o mt is only effective for channel 0. for other channels , it is fixed on mt=0. mt modulation frequency (hz) 0 0.183105468 1 2.014147656 2 3.173828125 3 4.211425781 4 5.126953125 5 5.859317000 6 6.347656250 7 7.080078125 register 2 default value : 00000 fffh bit type function 31 r/w keyboard split point ( ksp) 30:28 r/w pitch octave (oct) 27:26 r/w voice volume adjustment (vva) 25:16 r/w frequency number (fn) 15:12 r/w sustain level (sl) 11:10 r/w envelop flag (ef) 00:attack 01:overshoot 10:decay 11: release 9:0 r/w envelop attenuation (ea) n ksp 0 the pitch is higher than or equal to that of sample pitch 1 the pitch is lower than that of sample pitch o vva attenuation = -12*bit1 -6*bit0 (db) p fn f out = f wave * (fn + fm + 2 10 ) * 2 -8*ksp+oct-10 where f out = final output frequency f wave = frequency of sample wave register 3 default value : 00000000h bit type function 31:28 r/w key scale ratio (ksr) 27:24 r/w pan -low (stereo control) 23 r/w pan msb 22:16 r/w volume (vol) 15:12 r/w attack rate (ar) 11:8 r/w overshoot rate (or)
avance logic inc. ALS300 66 7:4 r/w decay rate (dr) 3:0 r/w release rate (rr) o pan table : (unit :db) pan left right pan left right 00 0 0 10 -96.0 -96.0 01 -1.5 0 11 0 -96.0 02 -3.0 0 12 0 -21.0 03 -4.5 0 13 0 -19.5 04 -6.0 0 14 0 -18.0 05 -7.5 0 15 0 -16.5 06 -9.0 0 16 0 -15.0 07 -10.5 0 17 0 -13.5 08 -12.0 0 18 0 -12.0 09 -13.5 0 19 0 -10.5 0a -15.0 0 1a 0 -9.0 0b -16.5 0 1b 0 -7.5 0c -18.0 0 1c 0 -6.0 0d -19.5 0 1d 0 -4.5 0e -21.0 0 1e 0 -3.0 0f -96.0 0 1f 0 -1.5 reference : 1. ddma : intel 82371ab d ata sheet. 2. pnp : plug and play isa specification ver 1.0a 3. dma : intel 8237 dma controller 4. pci audio : implementing legacy audio on the pci bus rev 2.1a 5. sb : als120 specification 6. ac97 : ac97 specification ver 1.03 7. pci : pci specification 2.1

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